78P2253-IGT Datasheet, PDF (2/23 Pages) List of Unclassifed Manufacturers – Transceiver

78P2253
E4/STM-1/STS-3/OC-3
Transceiver
FUNCTIONAL DESCRIPTION
The 78P2253 contains all the necessary transmit
and receive circuitry for connection between
139.264Mbit/s or 155.52Mbit/s signals and digital
Framer/Deframer ICs.
Operating Rate
The 78P2253 has a variety of operating modes and
rates. They are summarized in the tables below.
More detailed descriptions can be found in the
sections that follow.
Standard
E4/SONET CMI/ECL
Rate
(Mbit/s)
OC-3
0
STM1 optic
STS-3
0
STM-1 Coax
1
E4
1
0
155.52
1
155.52
0
139.264
1
139.264
Reference
Frequency
(MHz)
19.44
Active I/O
ECL
19.44
CMI
17.408
17.408
ECL
CMI
The digital interface of the 78P2253 can be either
Serial PECL, 4-bit Parallel CMOS or 8-bit Parallel
CMOS.
Mode PAR/SER
Serial
0
4-bit
1
Parallel
8-bit
1
Parallel
8BIT/BIT
X
0
1
Data pins
Clock
pins
TXDTP,N
RXDTP,N
TXDT[3:0]
RXDT[3:0]
TXDT[7:0]
RXDT[7:0]
TXCKP,N
RXCKP,N
TXCK
RXCK
TXCK
RXCK
Clock
Frequency
(MHz)
155.52( Sonet)
139.264 (E4)
38.88( Sonet)
34.816(E4)
19.44( Sonet)
17.408(E4)
Transmit timing is derived from either the reference
clock (the crystal oscillator or CKIN), or the
recovered receive clock. LLBACK and RLBACK
control the local and remote loopback modes
respectively.
LLBACK
0
1
X
X
RLBACK
0
0
1
X
HUB/HOST
1
1
1
0
Transmit Clock derived from
Reference
Reference
Receiver
Receiver
Medium Choices
The CMI/ECL pin selects one of two media for
transmission.
When the CMI/ECL pin is high, the chip is in CMI
mode and a 75Ω coaxial cable is used as the
transmission medium. In this mode, the CMIOUTP
and CMIOUTN pins are active. They connect the
chip to the coaxial cable through a transformer and
matching resistors. In CMI mode the transmitter
shapes the transmit pulses to meet the appropriate
template and the adaptive equalizer corrects the
received signal for dispersive attenuation. The
ECLOUTP and ECLOUTN pins are inoperative and
should be left open.
When the CMI/ECL pin is low the chip is in ECL
mode and a fiber optics transceiver is used. The
output data signal from the pins ECLOUTP and
ECLOUTN have PECL levels. In this mode, the CMI
pins are inoperative and should be left open. The
CMI encoder and decoder are disabled.
TRANSMITTER OPERATION
The transmitter section generates an analog signal
for transmission through a transformer onto the
coaxial cable or fiber optic module.
When the PAR/SER pin is low the chip is in serial
mode. Serial data is input to the 78P2253 on the
TXDTP and TXDTN pins at PECL levels. The data is
timed with the clock generated by the 78P2253 on
the TXCKP and TXCKN pins. In this mode the
8BIT/$BIT pin is ignored.
When the PAR/SER pin is high the chip is in parallel
mode. Parallel data is in put to the 78P2253 on the
TXDT[7:0] pins. The input data is timed with the
clock output from TXCK. When 8BIT/$BIT is high all
eight bits of TXDT[7:0] are used and the clock
frequency at TXCK is one-eighth the standard
frequency. When 8BIT/$BIT is low the lower four
bits, TXCK[3:0] are used and TXCK is one-fourth the
standard frequency.
The first bit output from the ECL/CMI interface is the
most significant bit on the parallel interface, TXDT7
in eight bit mode, TXDT3 in four bit mode.
The clock is generated by a phase-locked oscillator
(PLO). The PLO is locked to a crystal oscillator
operating at one-eighth of the standard clock
frequency, 19.44MHz for OC-3, STS-3 and STM-1
and 17.408MHz for E4. This is shown in Figure 1a.
An external clock signal at CKIN may also be
substituted for a crystal as the reference frequency
for the chip. In this mode, XTL1 and XTL2 must be
configured as shown in Figure 1b. Note that the chip
can be in either ECL or CMI mode when using either
an external clock or a crystal for the reference. In
serial mode the reference clock is output from
TXCK. In parallel mode, the parallel transmit clock is
output from TXCK.
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