HV7131RP Datasheet, PDF (19/79 Pages) List of Unclassifed Manufacturers – CMOS Image Sensor with Image Signal Processing

HV7131RP
Sensor Control B [SCTRB : 02h : 00h]
7
AE/AWB
Block
Sleep
6
Data path
Block
Sleep
5
Analog
Block
Sleep
4
All
Internal
Block
Sleep
0
0
0
0
3
Strobe
Signal
Enable
0
2
1
0
Clock Division
0
0
0
< Clock Acronym Definition >
MCF : Master Clock Frequency
SCF : Sensor Clock Frequency
VCF : Video Clock Frequency
< Clock Frequency Relation >
MCF : MCF
SCF : DCF/2
VCF : ICF*2 for 8bit output
DCF : Divided Clock Frequency
ICF : Image Processing Clock Frequency
LCF : Line Clock Frequency
DCF : MCF/Clock Division
ICF SCF for 3x3 interpolation,
SCF/2 for 1/4 subsampling mode
SCF/4 for 1/16 subsampling mode
LCF : 1/(HBLANK Period + HSYNC Period)
AE/AWB Block Sleep AE/AWB block goes into sleep mode with this bit set to high.
Data path Block Sleep Image processing data path block goes into sleep mode with this bit set to
high.
Analog Block Sleep all internal analog block goes into sleep mode with this bit set to high. With
All Digital Block Sleep active, sensor goes into power down mode.
All Internal Block
Sleep
all internal digital and analog block goes into sleep with this bit set to high.
Strobe Signal Enable When strobe signal is enabled by this bit, STROBE pin will indicates when
strobe light should be splashed in the dark environment to get adequate
lighted image.
Clock Division
divides input master clock(IMC) for internal use. Internal divided clock
frequency (DCF) is defined as master clock frequency (MCF) divided by
specified clock divisor. Internal divided clock frequency (DCF) is as
follows.
000 : MCF, 001 : MCF/2, 010 : MCF/4, 011 : MCF/8
2005/ 02 / 04 V1.5
- 19 -
2005 MagnaChip Semiconductor Ltd.
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