EUA5202 Datasheet, PDF (19/22 Pages) Eutech Microelectronics Inc – 2-W Stereo Audio Power Amplifier with Mute

EUA5202
Power Supply Decoupling, C_S
The EUA5202 is a high-performance CMOS audio
amplifier that requires adequate power supply
decoupling to ensure the output total harmonic distortion
(THD) is as low as possible. Power supply decoupling
also prevents oscillations for long lead lengths between
the amplifier and the speaker. The optimum decoupling
is achieved by using two capacitors of different types of
noise on the power supply leads. For higher frequency
transients, spikes, or digital hash on the line, a good low
equivalent – series - resistance (ESR) ceramic capacitor,
typically 0.1µF placed as close as possible to the device
V_DD lead works best. For filtering lower – frequency
noise signals, a larger aluminum electrolytic capacitor of
10 µF or greater placed near the audio power amplifier is
recommended.
Bypass Capacitor, C_B
The bypass capacitor, C_B, is the most critical capacitor
and serves several important functions. During startup or
recovery from shutdown mode, C_B determines the rate at
which the amplifier starts up. The second function is to
reduce noise produced by the power supply caused by
coupling into the output drive signal. This noise is from
the midrail generation circuit internal to the amplifier,
which appears as degraded PSRR and THD+N. Bypass
capacitor, C_B, values of 0.1 µF to 1 µF ceramic of
tantalum low-ESR capacitors are recommended for the
best THD and noise performance.
In Figure 2, the full feature configuration, two bypass
capacitors are used. This provides the maximum
separation between right and left drive circuits.When
absolute minimum cost and/or component space is
required, one bypass capacitor can be used as shown in
Figure 1. It is critical that terminals 6 and 19 be tied
together in this configuration.
Output Coupling Capacitor, C_C
In the typical single-supply SE configuration, and output
coupling capacitor (C_C) is required to block the dc bias
at the output of the amplifier thus preventing dc currents
in the load. As with the input coupling capacitor and
impedance of the load form a high-pass filter governed
by equation 6
fc(high)=
1
2 π R C ^{---------------------------- (6)}
LC
The main disadvantage, from a performance standpoint,
is the load impedances are typically small, which drives
the low-frequency corner higher degrading the bass
response. Large values of C_C are required to pass low
frequencies into the load. Consider the example where a
C_C of 330 µF is chosen and loads vary from 3Ω, 4Ω, 8Ω,
32Ω, 10kΩ, to 47kΩ. Table 1 summarizes the frequency
response characteristics of each configuration.
Table1. Common Load Impedances vs Low Frequency Output
Characteristics in SE Mode
R_L
C_C
Lowest Frequency
3Ω
330 µF
161 Hz
4Ω
330 µF
120 Hz
8Ω
330 µF
60 Hz
32 Ω
330 µF
15 Hz
10000 Ω 330 µF
0.05 Hz
47000 Ω 330 µF
0.01 Hz
As Table 1 indicates, most of the bass response is
attenuated into 4–Ω load, an 8–Ω load is adequate,
headphone response is good, and drive into line level
inputs (a home stereo for example) is exceptional.
Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this
applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series
with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor
in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an
ideal capacitor.
Bridged-tied Load Versus Single-ended Mode
Figure 56 show a linear audio power amplifier (APA) in
a BTL configuration. The EUA 5202 BTL amplifier
consists of two linear amplifiers driving both ends of the
load. There are several potential benefits to this
differential drive configuration, but initially consider
power to the load. The differential drive to the speaker
means that as one side is slewing up, the other side is
slewing down, and vice versa. This in effect doubles the
voltage swing on the load as compared to a ground
referenced load. Plugging 2 × V_O(PP) into the power
equation, where voltage is squared, yields 4 × the output
power from the same supply rail and load impedance
(see equation 7 )
V_(rms)
V
O(PP)
22
Power
2
V(rms)
------ (7)
R_L
DS5202 Ver 1.4 Nov. 2004
19