STK17T88 Datasheet, PDF (18/25 Pages) List of Unclassifed Manufacturers – nvTime Event Data Recorder 32K x 8 AutoStore nvSRAM With Real-Time Clock

STK17T88
the user after t_HRECALL delay (See AutoStore™
/POWER-UP RECALL) after V_CC has been restored
to the device.
INTERRUPTS
The STK17T88 provides three potential interrupt
sources. They include the watchdog timer, the power
monitor, and the clock/calendar alarm. Each can be
individually enabled and assigned to drive the INT pin.
In addition, each has an associated flag bit that the
host processor can use to determine the cause of the
interrupt.
Some of the sources have additional control bits that
determine functional behavior. In addition, the pin
driver has three bits that specify its behavior when an
interrupt occurs. A functional diagram of the interrupt
logic is shown below.
Watchdog
Timer
Power
Monitor
VINT
Clock
Alarm
WDF
WIE
PF
PFE
AF
AIE
P/L
Pin
Driver
H/L
VCC
INT
VSS
Figure 8. Interrupt Block Diagram
The three interrupts each have a source and an
enable. Both the source and the enable must be
active (true high) in order to generate an interrupt
output. Only one source is necessary to drive the pin.
The user can identify the source by reading the
Flags/Control register, which contains the flags
associated with each source. All flags are cleared to 0
when the register is read. The cycle must be a
complete read cycle ( WE high); otherwise the flags
will not be cleared. The power monitor has two pro-
grammable settings that are explained in the power
monitor section.
Once an interrupt source is active, the pin driver
determines the behavior of the output. It has two
programmable settings as shown below. Pin driver
control bits are located in the Interrupts register.
According to the programming selections, the pin can
be driven in the backup mode for an alarm interrupt.
In addition, the pin can be an active low (open-drain)
or an active high (push-pull) driver. If programmed for
operation during backup mode, it can only be active
low. Lastly, the pin can provide a one-shot function so
that the active condition is a pulse or a level condition.
In one-shot mode, the pulse width is internally fixed at
approximately 200 ms. This mode is intended to reset
a host microcontroller. In level mode, the pin goes to
its active polarity until the Flags/Control register is
read by the user. This mode is intended to be used as
an interrupt to a host microcontroller. The control bits
are summarized as follows:
Watchdog Interrupt Enable - WIE. When set to 1, the
watchdog timer drives the INT pin as well as an
internal flag when a watchdog time-out occurs. When
WIE is set to 0, the watchdog timer affects only the
internal flag.
Alarm Interrupt Enable - AIE. When set to 1, the alarm
match drives the INT pin as well as an internal flag.
When set to 0, the alarm match only affects to internal
flag.
Power Fail Interrupt Enable - PFE. When set to 1, the
power fail monitor drives the pin as well as an internal
flag. When set to 0, the power fail monitor affects only
the internal flag.
High/Low - H/L. When set to a 1, the INT pin is active
high and the driver mode is push-pull. The INT pin
can drive high only when V_CC>V_switch. When set to a 0,
the INT pin is active low and the drive mode is open-
drain. Active low (open drain) is operational even in
battery backup mode.
Pulse/Level - P/L. When set to a 1 and an interrupt
occurs, the INT pin is driven for approximately 200
ms. When P/L is set to a 0, the INT pin is driven high
or low (determined by H/L) until the Flags/Control
register is read.
When an enabled interrupt source activates the INT
pin, an external host can read the Flags/Control reg-
ister to determine the cause. Remember that all flags
will be cleared when the register is read. If the INT pin
is programmed for Level mode, then the condition will
clear and the INT pin will return to its inactive state. If
the pin is programmed for Pulse mode, then reading
the flag also will clear the flag and the pin. The pulse
will not complete its specified duration if the
Flags/Control register is read. If the INT pin is used as
a host reset, then the Flags/Control register should
not be read during a reset.
April 2005
18
Document Control #ML0024 rev 1.2