ARM946E-S Datasheet, PDF (173/218 Pages) List of Unclassifed Manufacturers – TECHNICAL REFERENCE MANUAL

Test Support
Table 10-1 and Table 10-2 show how the registers are used. The pause bits from the
BIST control register provide extra decode of these registers.
Table 10-1 Instruction BIST address and general registers
BIST register
IBIST address register
IBIST address register
IBIST general register
IBIST general register
IBIST
Read
pause
0
IBIST fail address
1
IBIST fail address
0
IBIST fail data
1
IBIST peek data
Write
IBIST start address
IBIST peek/poke address
IBIST seed data
IBIST poke data
Table 10-2 Data BIST address and general registers
BIST register
DBIST address register
DBIST address register
DBIST general register
DBIST general register
IBIST
Read
pause
0
DBIST fail address
1
DBIST fail address
0
DBIST fail data
1
DBIST peek data
Write
DBIST start address
DBIST peek/poke address
DBIST seed data
DBIST poke data
10.3.3 Pause modes
ARM Ltd. recommends that you use the following production test sequence for the
compiled RAM:
1. Test each RAM using a full test.
2. Test the BIST hardware for each RAM.
To allow testing of the BIST hardware, it is necessary to deliberately corrupt data in the
SRAM. This can be done by the ATPG tool if is recognizes the SRAM parameters.
Alternatively a pause mechanism enables you to halt the BIST test. This enables you to
corrupt data within the RAM. The sequence for this is:
1. Write the address for the location to be corrupted with an MCR to the relevant BIST
address register.
2. Write the corrupted data using a MCR to the BIST general register.
ARM DDI 0201A
Copyright © 2001 ARM Limited. All rights reserved.
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