M6759_1 Datasheet, PDF (17/33 Pages) List of Unclassifed Manufacturers – 8-bit MTP Micro-controller

Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
Bit
Description
7
TF2, Timer 2 Overflow Flag. Hardware will set TF2 when the Timer 2 overflow from FFFFH, TF2 must be
cleared to 0 by software. TF2 will only be set to 1 if RCLK and TCLK are both cleared to 0. Writing a 1 to
TF2 forces a Timer 2 interrupt if enabled.
6
EXF2, Timer 2 External Flag. Hardware will set EXF2 when a reload or capture is caused by a high-to-low
transition on the T2EX pin, and EXEN2 is set. EXF2 must be cleared to 0 by software. Writing a 1 to EXF2
forces a Timer 2 interrupt if enable.
5
RCLK, Receive Clock Flag. Determine whether Timer 1 or Timer 2 is used for Serial Port 0 timing of
receive data in serial mode 1 or 3. RCLK=1 selects Timer 2 overflow as the receive clock. RCLK=0 selects
Timer 1 overflow as the receive clock.
4
TCLK, Transmit Clock Flag. Determine whether Timer 1 or Timer 2 is used for Serial Port 0 timing of
transmit data in serial mode 1 or 3. RCLK=1 selects Timer 2 overflow as the transmit clock. RCLK=0
selects Timer 1 overflow as the transmit clock.
3
EXEN2, Timer 2 External Enable. EXEN2=1 enables capture or reload to occur as a result of high-to-low
transition on T2EX, if Timer 2 is not generating baud rates for the serial port. EXEN2=0 causes Timer 2 to
ignore all external events at T2EX.
2
TR2, Timer 2 Run Control Flag. TR2=1 starts Timer 2, TR2=0 stops Timer 2.
1
C/T2 Counter/Timer Selector. C/T2=0 selects a timer function for Timer 2. C/T2=1 selects a counter of
falling transitions on the T2 pin. When used as a timer, Timer 2 run at 4 clocks per tick or 12 clocks per tick
as programmed by CKCON.5, in all modes except baud rate generator mode. When used in baud rate
generator mode, Timer 2 runs at 2 clocks per tick, independent of state of CKCON.5
0
CP/RL2, Capture/Reload Flag. When CP/RL2=1, Timer 2 captures occur on high-to-low transitions of
T2EX, if EXEN2=1. When CP/RL2=0, auto-reloads occur when Timer2 overflows or when high-to-low
transitions occur on T2EX, if EXEN2=1. If either RCLK or TCLK is set to 1, CP/RL2 will not function and
Timer 2 will operate in auto-reload mode following each overflow.
SFR 98H : SCON Register
Bit
Description
7-6
SM1,SM0, Serial Port 0 Mode Select bits
SM1
0
0
1
1
SM0
0
1
0
1
Mode
0
1
2
3
5
SM2, Multiprocessor Communication Enable. In modes 2 and 3, this bit enables the multiprocessor
communication feature. If SM2=1 in mode 2 or 3, the RI will not be activated if the received 9^th bit is 0. If
SM2=1 is in mode 1, then RI will only be activated if a valid stop is received. In mode 0, SM2 establishes
the baud rate: when SM2=0, the baud rate is clk/12; when SM2=1, the baud rate is clk/4.
4
REN, Receive Enable. When REN=1, reception is enabled.
3
TB8, Defined the state of the 9^th data bit transmitted in modes 2 and 3.
2
RB8, In modes 2 and 3, RB8 indicates the state of the 9^th bit received. In mode 1, RB8 indicates the state
of received stop bit. In mode 0, RB8 is not used.
1
TI, Transmit Interrupt Flag. Indicates that the transmit data word has been shifted out. In mode 0, TI is set
at the end of the 8^th data bit. In all other modes, TI is set when the stop bit is placed on the TXD pin, TI must
be cleared by software.
0
RI, Receive Interrupt Flag. Indicates that serial data word has been received. In mode 0, RI is set at the
end of the 8^th data bit. In mode 1, RI is set after the last sample of the incoming stop bit, subject to the state
of SM2. In modes 2 and 3, RI is set at the end of the last sample of RB8, RI must be cleared by the
software.
16
Ver.1.01, Doc. No.: 6759DS02.doc
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