GL811USB Datasheet, PDF (17/36 Pages) List of Unclassifed Manufacturers – USB 2.0 to ATA / ATAPI Bridge Controller

GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller
3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3.2 Device negates IORDY before t_A, but causes IORDY to be asserted before t_A. IORDY is
released prior to negation and may be asserted for no more than 5 ns before release: no
wait generated.
3.3 Device negates IORDY before t_A, IORDY is released prior to negation and may be
asserted for no more than 5 ns before release: wait generated. The cycle completes after
IORDY is released. For cycles where a wait is generated and DIOR_ is asserted, the
device shall read data on IODD(0:7) for t_RD before asserting IORDY.
4.DMACK_ shall remain negated during a register transfer.
Register transfer timing parameters
t₀ Cycle time
t₁ Address valid to DIOR_/ DIOW_ setup
t₂ DIOR_/ DIOW_ pulse width 8-bit
t_2i DIOR_/ DIOW_ recovery time
t₃ DIOW_ data setup
t₄ DIOW_ data hold
t₅ DIOR_ data setup
t₆ DIOR_ data hold
t_6Z DIOR_ data tristate
t₉ DIOR_/ DIOW_ to address valid hold
Read Data Valid to IORDY active
t_RD
(if IORDY initially low after t_A)
t_A IORDY Setup time
t_B IORDY Pulse Width
t_C IORDY assertion to release (max)
Timing (ns)
2000
1000
300
900
80
40
-
-
-
900
-
-
-
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