73K324BL Datasheet, PDF (17/34 Pages) List of Unclassifed Manufacturers – Single-Chip Modem w/Integrated Hybrid

73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
CONTROL REGISTER 2
D7
D6
D5
D4
D3
D2
D1
D0
CR2 0
100
BIT
D0
D1
SPEC
REG
ACCESS
NAME
Equalizer
Enable
Train Inhibit
CALL
INIT
TRANSMIT
S1
16 WAY
RESET
DSP
TRAIN EQUALIZER
INHIBIT
ENABLE
CONDITION
0
1
0
1
DESCRIPTION
The adaptive equalizer is in its initialized state.
The adaptive equalizer is enabled. This bit is used in
handshakes to control when the equalizer should
calculate its coefficients.
The adaptive equalizer is active.
The adaptive equalizer coefficients are frozen.
D2
RESET DSP
0
The DSP is inactive and all variables are initialized.
1
The DSP is running based on the mode set by other
control bits.
D3
16 Way
0
The receiver and transmitter are using the same decision
plane (based on the modulator control mode).
1
The receiver, independent of the transmitter, is forced
into a 16 point decision plane. Used for QAM
handshaking.
D4
Transmit S1
0
The transmitter when placed in alternating mark/space
mode transmits 0101...... scrambled or not dependent on
the bypass scrambler bit.
1
When this bit is 1 and only when the transmitter is placed
in alternating mark/space mode by CR1 bits D7, D6, and
in DPSK or QAM, an unscrambled repetitive double di-bit
pattern of 00 and 11 at 1200 bps (S1) is sent
D5
Call Init
0
The DSP is set-up to do demodulation and pattern
detection based on the various mode bits. Both answer
tones are detected in demodulation mode concurrently;
TR-D0 is ignored.
1
The DSP decodes unscrambled mark, answer tone and
call progress tones.
D6
Special
0
Normal CR3 access.
Register
Access
1
Setting this bit and addressing CR3 allows access to the
special register (see the special register for details).
D7
Not used at this time
0
Only write zero to this bit.
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