VS1000 Datasheet, PDF (15/23 Pages) List of Unclassifed Manufacturers – Ogg Vorbis Player IC with USB and NAND FLASH Interface

VLSI
Solution ^y
VS1000b
VS1000
7. FIRMWARE OPERATION
7 Firmware Operation
The firmware uses the following pins (see the example schematics in Section 5):
Pin
PWRBTN
GPIO0 0
GPIO0 1
GPIO0 2
GPIO0 3
GPIO0 4
GPIO0 6
GPIO0 7
NFCE
XCS
SI
SO
USBN
USBP
Description
High level starts regulator, is also read as the Power button Key.
external 1 MΩ pull-down resistor, Key 1 connects a 100 kΩ pull-up resistor
external 1 MΩ pull-down resistor, Key 2 connects a 100 kΩ pull-up resistor
external 1 MΩ pull-down resistor, Key 3 connects a 100 kΩ pull-up resistor
external 1 MΩ pull-down resistor, Key 4 connects a 100 kΩ pull-up resistor
external 1 MΩ pull-down resistor, Key 5 connects a 100 kΩ pull-up resistor
external pull-down resistor for USB Mass Storage Device, pull-up for USB Audio Device
external pull-down resistor for 1.8 V I/O voltage, pull-up resistor for 3.3 V I/O voltage
external pull-up resistor for normal operation, pull-down to use RAM disk for UMS Device
external pull-up to enable SPI EEPROM boot
Power LED control during firmware operation
Feature LED control during firmware operation
external 1 MΩ pull-up
external 1 MΩ pull-up
Boot order:
Stage
Power on
Reset
UART Boot
SPI EEPROM Boot
NAND FLASH probed
Default firmware
Description
Power button (PWRBTN) pressed when VHIGH has enough voltage
Power-on reset, XRESET, or watchdog reset causes software restart
Almost immediately after power-on UART can be used to enter emulator mode.
If XCS is high, SPI Boot is tried.
If NFCE is high, NAND FLASH is checked.
The firmware in ROM takes control.
7.1 SPI Boot
The first boot method is SPI EEPROM. If GPIO1 0 is low after reset, SPI boot is skipped. If GPIO1 0 is high, it is
assumed to have a pull-up resistor and SPI boot is tried.
First the first four bytes of the SPI EEPROM are read using 16-bit address. If the bytes are “VLSI”, a 16-bit
EEPROM is assumed and the boot continues. If the last 3 bytes are read as “VLS”, a 24-bit EEPROM is assumed
and boot continues in 24-bit mode. Both 16-bit and 24-bit EEPROM should have the “VLSI” string starting at
address 0, and the rest of the boot data starting at address 4. If no identifier is found, SPI EEPROM boot is
skipped.
Boot records are read from EEPROM until an execute record is reached. Unknown records are skipped using the
data length field.
Byte Description
0
type 0=I-mem 1=X-mem 2=Y-mem 3=execute
1,2 data len lo, hi – data length in bytes
3, 4 address lo, hi – record address
5.. data*
Version 1.0, 2007-09-11
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