ZXCW8100 Datasheet, PDF (14/24 Pages) List of Unclassifed Manufacturers – 32 BIT STEREO DIRECT DRIVE DIGITAL AUDIO AMPLIFIER

ZXCW8100S28
Mute
SPI REGISTER SUMMARY
Mute is enabled with the MUTE pin. Mute is active low.
Master clock
The system master clock is applied to pin M-CK
Output drive
The following indicates the general structure of the 72
bit SPI word used for control and data.
Control
SPI preamble:
ca1 ca0 1 00011 read
ca1 ca0 1 00010 write
Output drive is provided on 8 pins, 4 each for left and
right. For each channel the pins are OP1 to OP4 then L
or R. OP1 and OP2 as a pair drive the gates of an N & P
channel MOSFET pair through a gate drive buffer that
includes dead time control. OP3 and OP4 drive a similar
pair. These pairs in turn drive a BTL (bridge tied load)
loudspeaker – see the Typical Applications Diagram for
details. Timing diagrams are shown in the AC
Characteristics section.
Bits ca1 and ca0 should be set low. The next 4 bits are a
silicon reference to the ZXCW8100 part number. The
other two bits determine if the SPI interface is in read or
write modes.
Operating mode
Direct drive no
dead time
Direct drive
with dead time
MODE0 pin
0
1
MODE1 pin
0
0
Mode (dead/no dead time)
MODE0 and MODE1 are used to set the operating
mode of the ZXCW8100 device. There are two modes
available, direct drive with and without dead time.
Without dead time the output stage on and off
switching to the N and P channel MOSFETs occurs at
the same time. The user can then design any dead time
or cross conduction into the output stage as required
by the characteristics of the MOSFET being used.
When dead time is selected a delay is introduced
between the N and P channel MOSFET switching such
that the active MOSFET is switched off before the
inactive MOSFET is switched on. This is particularly
useful where MOSFETs have a slow turn off time and
might otherwise give a large amount of cross
conduction in the N and P channel MOSFET pair.
Dead time is a function of the master clock frequency
and is effectively a half the master clock rate. For the
nominal 33MHz master clock, dead time is therefore
approximately 15ns.
Whilst this digital dead time is available it is
recommended for most applications that shorter
periods of dead time are used by including dead time
control within the FET drive buffer circuit.
SEMICONDUCTORS
ISSUE 3 - NOVEMBER 2003
14