G768B Datasheet, PDF (14/15 Pages) List of Unclassifed Manufacturers – Remote/Local Temperature Sensor, 2 Fan Controllers with SMBus Serial Interface and System Reset Circuit

Global Mixed-mode Technology Inc.
G768B
Slave Addresses
The G768B appears to the SMBus as one device hav-
ing a common address for all the ADC and fan control
channels. The device address is fixed to be 7Ah for
write and 7Bh for read.
The G768B also responds to the SMBus Alert Response
slave address (see the Alert Response Address section).
POR and UVLO
The G768B has a volatile memory. To prevent am-
biguous power-supply conditions from corrupting the
data in memory and causing erratic behavior, a POR
voltage detector monitors Vcc and clears the memory
if Vcc falls below 1.7V (typical, see Electrical Charac-
teristics table). When power is first applied and Vcc
rises above 1.75V (typical), the logic blocks begin op-
erating, although reads and writes at V_CC levels below
3V are not recommended. A second Vcc comparator,
the ADC UVLO comparator, prevents the ADC from
converting until there is sufficient headroom (Vcc =
2.8V typical).
Power-Up Defaults:
„Interrupt latch is cleared.
„ADC begins auto /converting at a 0.25Hz rate.
„Command byte is set to 00h to facilitate quick re-
mote Receive Byte queries.
„THIGH and TLOW registers are set to max and
min limits, respectively.
SMBCLK
A
B
t_LOW
t_HIGH
C
D
EF
G
H
IJ
K
LM
SMBDATA
t_SU:STA t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO t_BUF
Figure 6. SMBus Write Timing Diagram
A = start condition
B = MSB of address clocked into slave
C = LSB of address clocked into slave
D = R / W bit clocked into slave
E = slave pulls SMBData line low
F = acknowledge bit clocked into master
G = MSB of data clocked into slave
H = LSB of data clocked into slave
I = slave pulls SMBDATA line low
J = acknowledge clocked into master
K = acknowledge clocked pulse
L = stop condition data executed by slave
M = new start condition
SMBCLK
A
B
C
D
EF
G
t_LOW t_HIGH
SMBDATA
t_SU:STA t_{HD :STA}
t_{SU :DA T}
H
I
J
K
t_{SU :ST O}
t_BUF
Figure 7. SMBus Read Timing Diagram
A = start condition
B = MSB of address clocked into slave
C = LSB of address clocked into slave
D = R / W bit clocked into slave
E = slave pulls SMBDATA line low
F =acknowledge bit clocked into master
G = MSB of data clocked into master
H = LSB of data clocked into master
I = acknowledge clocked pulse
J = stop condition
K= new start condition
Ver: 1.3
Oct 28, 2002
TEL: [phone]
http://www.gmt.com.tw
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