RTL8305SC Datasheet, PDF (131/160 Pages) List of Unclassifed Manufacturers – SINGLE-CHIP 5-PORT 10/100MBPS SWITCH CONTROLLER WITH DUAL MII INTERFACES

RTL8305SC
Datasheet
8.3.4. SMI
The SMI (Serial Management Interface) is also known as the MII Management Interface, and consists of
two signals (MDIO and MDC). It allows external devices with SMI master mode (MDC is output) to
control the state of the PHY and internal registers (SMI slave mode: MDC is input). MDC is an input
clock for the RTL8305SC to latch MDIO on its rising edge. The clock can run from DC to 25MHz.
MDIO is a bi-directional connection used to write data to, or read data from the RTL8305SC. The PHY
address is from 0 to 4.
Table 145. SMI Read/Write Cycles
Preamble Start OP Code PHYAD
REGAD
Turn Around
Data Idle
(32 bits) (2 bits) (2 bits)
(5 bits)
(5 bits)
(2 bits)
(16 bits)
Read 1……..1 01
10
A₄A₃A₂A₁A₀ R₄R₃R₂R₁R₀
Z0
D₁₅…….D₀ Z*
Write 1……..1 01
01
A₄A₃A₂A₁A₀ R₄R₃R₂R₁R₀
10
D₁₅…….D₀ Z*
Note: Z*: high-impedance. During idle time MDIO state is determined by an external 1.5KΩ pull-up resistor.
The RTL8305SC supports Preamble Suppression, which allows the MAC to issue Read/Write Cycles
without preamble bits. However, for the first cycle of MII management after power-on reset, a 32-bit
preamble is needed.
To guarantee the first successful SMI transaction after power-on reset, the external device should delay at
least 1second before issuing the first SMI Read/Write Cycle relative to the rising edge of reset.
8.3.5. Head-Of-Line Blocking
The RTL8305SC incorporates an advanced mechanism to prevent Head-Of-Line blocking problems when
flow control is disabled. When the flow control function is disabled, the RTL8305SC first checks the
destination address of the incoming packet. If the destination port is congested, the RTL8305SC will
discard this packet to avoid blocking the next packet, which is going to a non-congested port.
8.3.6. Port-Based VLAN
If the VLAN function is enabled by pulling down the strapping pin DisVLAN, the default VLAN
membership configuration by internal register is port 4 overlapped with all the other ports to form four
individual VLANs. This default configuration of the input port could be modified via an attached serial
EEPROM or SMI interface. The 16 VLAN membership registers designed into the RTL8305SC provide
full flexibility for users to configure the input ports to associate with different VLAN groups. Each input
port can join more than one VLAN group.
5-port 10/100Mbps Single-Chip Dual MII Switch Controller 119
Track ID: JATR-1076-21 Rev. 1.2