TXC-02050 Datasheet, PDF (13/28 Pages) List of Unclassifed Manufacturers – MRT Device 6-,8-,34-Mbit Line Interface TXC-0250

Terminal Side Timing Characteristics
Figure 6. NRZ Transmit Input
t_CYC
t_PWH
CLKI
1.4V
t_SU t_H
TP,TD
DATA
VALID
DATA
VALID
DATA
VALID
MRT
Parameter
Symbol
Min
Typ
Max
Unit
CLKI clock period
t_CYC
Note 2
ns
CLKI duty cycle (t_PWH/t_CYC)
--
45
55
%
TP,TD set-up time to CLKI↑
t_SU
3
ns
TP,TD hold time after CLKI↑
t_H
2
ns
Note 1: CLKI symmetry is measured about the 1.4VDC threshold in order to assure symmetric output waveforms.
Note 2: The clock input can be 6, 8, or 34 MHz (refer to page 5).
Figure 7. NRZ Receive Output
t_PWH ^tCYC
CLKO
RP,RD
t_OD(1)
t_OD(2)
CV
Parameter
Symbol
Min
CLKO clock period
t_CYC
CLKO duty cycle (t_PWH/t_CYC)
--
45
RP,RD output delay after CLKO↓
t_OD(1)
-5
CV output delay after CLKO↓
t_OD(2)
-5
Note 1: CKLO symmetry is measured about the 50% amplitude point.
Note 2: The clock output can be 6, 8, or 34 MHz (refer to page 4).
Typ
Note 2
Max
Unit
ns
55
%
5
ns
5
ns
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TXC-02050-MB
Ed. 3, April 1994