TM128160CKFWG Datasheet, PDF (13/26 Pages) List of Unclassifed Manufacturers – SPECIFICATION FOR LCD MODULE

6.4 Instruction code
Instruction List
Upper Code
Lower Code
Exe
Reg. Register
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
cu-
No. Name
R/ RS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description
tion
W
Cyc
le
IR Index
0 0 * * * * * * * * * ID6 ID5 ID4 ID3 ID2 ID1 ID0 Sets the index register value.
0
Note1
SR Status read 1
0 L7 L6 L5 L4 L3 L2 L1 L0 0 C6 C5 C4 C3 C2 C1 C0 Reads the driving raster-row
0
position (L7–0) and contrast setting
(C6–0).
R00h Start
0 1 * * * * * * * * * * * * * * * 1 Starts the oscillation mode.
oscillation
10 Note1
ms
Device
1 1 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 Reads 0766H.
0
code read
R01h Driver
output
control
0 1 0 0 0 0 0 0 CM SGS 0 0 0 NL4 NL3 NL2 NL1 NL0 Sets the common driver shift
0
S
direction (CMS), segment driver
shift direction (SGS) and driving
duty ratio (NL4–0).
R02h LCD-
0 1 0 0 0 0 0 RST B/C EOR 0 0 NW NW NW NW NW NW Sets LCD drive AC waveform
0
driving-
5 4 3 2 1 0 (B/C), and EOR output (EOR) or the
waveform
number of n-raster-rows (NW5–0)
control
at C-pattern AC drive.
R03h Power
control 1
0 1 BS3 BS2 BS1 BS0 BT3 BT2 BT1 BT0 0 DC2 DC1 DC0 AP1 AP0 SLP STB Sets the sleep mode (SLP), standby 0
mode (STB), LCD power on (AP1–
0), boosting cycle (DC2–0),
boosting output multiplying factor
(BT2–0), operation of voltage
inverting circuit (BT3) and LCD
drive bias value (BS3–0).
R04h Contrast
control
0 1 0 0 0 0 0 VR2 VR1 VR0 0 CT6 CT5 CT4 CT3 CT2 CT1 CT0 Sets the regulator adjustment (VR2– 0
0) and contrast adjustment (CT6–0).
R05h Entry mode 0 1 SPR 0 0 0 0 0 HWM 0 0 0 I/D1 I/D0 AM LG2 LG1 LG0 Specifies AC counter mode (AM), 0 Note2
increment/decrement mode (I/D1–
0), high-speed write mode (HWM).
R06h Compare
0 1 CP1 CP1 CP1 CP1 CP1 CP1 CP9 CP8 CP7 CP6 CP5 CP4 CP3 CP2 CP1 CP0 Specifies the compare resister
0
Resister
543210
(CP15-0),
R07h Display
control
0 1 0 0 0 0 0 VLE2 VLE1 SPT 0 0 0 0 B/W REV D1 D0 Specifies display on (D1-0), black- 0
and-white reversed display (REV),
pixel on/off mode (ALB), screen
division driving (SPT) and vertical
scroll .(VLE2-1)
R0Bh Frame
0 1 0 0 0 0 0 0 DIV DIV 0 0 0 0 RTN RTN RTN RTN Specifies the line retrace period
0
frequency
10
3 2 1 0 (RTN3–0) and operating clock
control
frequency division ratio (DIV1–0).
R0Ch Power
control 2
R11h Vertical
scroll
control
R14h 1^st screen
driving
position
R15h 2^nd screen
driving
position
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 VC2 VC1 VC0 Sets the adjustment factor for the 0
Vci voltage (VC2–0).
0 1 VL2 VL2 VL2 VL2 VL2 VL2 VL2 VL2 VL1 VL1 VL1 VL1 VL1 VL1 VL1 VL1 Sets the 1^st screen display start
0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 raster- row (VL17-10) and 2^nd
screen display start raster-row
(VL27-20).
0 1 SE SE SE SE SE SE SE SE SS SS SS SS SS SS SS SS Sets the 1^st screen driving start
0
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10 position (SS17–10) and 1^st screen
driving end position (SE17–10).
0 1 SE SE SE SE SE SE SE SE SS SS SS SS SS SS SS SS Sets 2^nd screen driving start position 0
27 26 25 24 23 22 21 20 27 26 25 24 23 22 21 20 (SS27–20) and 2^nd screen driving
end position (SE27–20).
R16h Horizontal 0
RAM
address
position
1 HE HEA HEA HEA HEA HEA HEA HEA HSA HSA HSA HSA HSA HSA HSA HSA Sets start (HSA7–0) and end
0
A7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 (HEA7–0) of the horizontal RAM
address range.
R17h Vertical
0 1 VEA VEA VEA VEA VEA VEA VEA VEA VSA VSA VSA VSA VSA VSA VSA VSA Sets start (VSA7–0) and end
0
RAM
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 (VEA7–0) of the vertical RAM
address
address range.
position
R20h RAM write 0
data mask
1 WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM Specifies write data mask (WM15– 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0) at RAM write.
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