STAC9708 Datasheet, PDF (13/56 Pages) List of Unclassifed Manufacturers – Multi-Channel AC97 Codec With Multi-Codec Option

SigmaTel, Inc.
Preliminary
STAC9708/11
2.1 Clocking
STAC9708/11 derives its clock internally from an externally connected 24.576 MHz crystal or an
oscillator through the XTAL_IN pin. Synchronization with the AC'97 controller is achieved through the
BIT_CLK pin at 12.288 MHz (half of crystal frequency).
The beginning of all audio sample packets, or “Audio Frames”, transferred over AC-Link is
synchronized to the rising edge of the “SYNC” signal driven by the AC'97 controller. Data is
transitioned on AC-Link on every rising edge of BIT_CLK, and subsequently sampled by the receiving
side on each immediately following falling edge of BIT_CLK.
2.2 Reset
There are 3 types of resets as detailed under “Timing Characteristics”.
1. a “cold” reset where all STAC9708/11 logic and registers are initialized to their default state
2. a “warm” reset where the contents of the STAC9708/11 register set are left unaltered
3. a “register” reset which only initializes the STAC9708/11 registers to their default states
After signaling a reset to the STAC9708/11, the AC'97 controller should not attempt to play or capture
audio data until it has sampled a “Codec Ready” indication via register 26h from the STAC9708/11.
For proper reset operation SDATA_OUT should be “0” during “cold” reset.
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