GLT5160L16 Datasheet, PDF (13/45 Pages) List of Unclassifed Manufacturers – 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM

Burst Interruption
[Read Interrupted by Read]
The burst read operation can be interrupted by a new read of the
same or the other bank. GLT5160L16 allows random column
access. READ to READ interval is 1 CLK minimum.
CLK
Command
A[9:0]
A[10]
BA
DQ
REA
Yi
0
0
REA
Yj
0
0
READ
READ
Yk
Yl
0
0
1
0
Qi0
Qj0
Qj1
Qk0
Qk1
Qk2
Ql0
Ql1
Ql2
Ql3
Internal Precharge Start Timing
Figure 9. READ Interrupted by READ (BL=4, CL=3)
[Read Interrupted by Write]
Burst read operation can be interrupted by write of the same or the
other bank. Random column access is allowed. In this case, the DQ
should be controlled adequately by using the DQMU / DQML to
prevent the bus contention. The output is disabled automatically 2
cycles after WRITE assertion.
CLK
Command
A[9:0]
A[10]
BA
DQMU,
Q
D
REA
Yi
0
0
WRITE
Yj
0
0
Qi0
DQM U/ DQML control
Write control
Dj0
Dj1
Dj2
Dj3
Figure 10. READ Interrupted by WRITE (BL=4, CL=3)
G-LINK Technology
13
DEC. 2003 (Rev.2.4)