XE1202 Datasheet, PDF (12/26 Pages) List of Unclassifed Manufacturers – Low-power, integrated UHF transceiver

t_bit
datain
no filtering
IN _{freq_synth}
Data Sheet
XE1202
staircase filtering
t_rise
IN _{freq_synth}
Figure 4 Modulation without and with pre-filtering
The characteristic of the smoothing filter is the ratio t_rise/t_bit. The value of this ratio is programmable with the register
“RTParam_Stair”, as shown in the following table.
FSParam_Stair
0
1
t_rise/t_bit
10 %
20 %
4.1.6 Pattern recognition
XE1202 includes a pattern recognition function. When “ADParam_Pattern” (see the Configuration register section
below) is set to “1” this feature is turned on, provided the bit synchronizer is turned on too (the pattern recognition
feature doesn’t work if the bit synchronizer is turned off). In this case, the incoming NRZ bit stream is compared
with a pattern stored in the “Pattern” register. The length of this pattern can be 8, 16, 24, or 32 bits, as defined by
“ADParam_Psize”. When comparing the streams 0, 1, 2, or 3 errors, as defined by “ADParam_Psize” can be
allowed to detect a match. The PATTERN output is driven by the output of this comparator. It is “high” when a
match is detected, otherwise “low”.
When the feature is disabled, the PATTERN output is set to “low”
4.1.7 Clock Output for external processor
When “RTParam_Clkout” is set high, a frequency divider by 4, 8, 16, or 32, depending on “ADParam_Clkfreq” (see
the Configuration register section below), is embedded in XE1202 and provides the CLKOUT clock signal for an
MCU or an external circuitry. The input frequency is the 39.0 MHz reference frequency, so the possible clocks
available on CLKOUT are 1.22, 2.44, 4.87, or 9.75 MHz. When the XE1202 is in Sleep Mode (MODE[2:0] = 000),
this clock is stopped.
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