W7020 Datasheet, PDF (12/36 Pages) List of Unclassifed Manufacturers – Bluetooth Radio Module

W7020 Bluetooth Radio Module
Preliminary Data Sheet
September 2000
Serial Interface
The serial interface implementation is based on the boundary-scan architecture, IEEE Std. 1149.1. Figure 4
shows a block diagram of the serial interface. It is identical to the boundary-scan architecture if the extra control
signals from the controller access port (CAP) block are removed.
The interconnection between the serial interface and the external controller (baseband chip) consists of four 1-bit
signals: control data input (CDI), control mode select (CMS), control clock (CLK), and control data output (CDO).
The CDI signal transports serial data to the W7020, while the CDO signal transports serial data out of the
W7020.
DATA BUS (D[7:0])
CDI
UPDATE_DR
SHIFT_DR
CMS
CLK
CAP
CONTROL
CLOCK_DR
ENABLE
CDO
UPDATE_IR
SHIFT_IR
CLOCK_IR
SELECT
DATA REGISTER
BYPASS
REGISTER
DECODE
INSTRUCTION
REGISTER
STATUS
BUS
ENABLE
CONTROL
ADDRESS
Figure 4. Slave Serial Interface (IEEE Std. 1149.1)
The CAP is a controller-state machine and is controlled by the CLK and CMS signals. The CAP, which consists
of 16 states, determines whether an instruction register scan or a data register scan will be performed. In these
two register scan cycles, data are exchanged between the interconnected units. The interface architecture
contains three types of registers: instruction register (IR), bypass register (BYP), and data register (DR).
The structure of the instruction register is shown in Figure 5. The register has a serial data input (CDI) and serial
data output (CDO), as well as parallel status inputs and outputs. During a scan period, serial data are shifted
through the register. Shadow latches are needed to hold the parallel output at a steady value when shifting
occurs. The width of the instruction register is 6 bits.
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Lucent Technologies Inc.