U632H16 Datasheet, PDF (12/15 Pages) List of Unclassifed Manufacturers – PowerStore 2K x 8 nvSRAM

U632H16
1. Read address 000 (hex) Valid READ
2. Read address 555 (hex) Valid READ
3. Read address 2AA (hex) Valid READ
4. Read address 7FF (hex) Valid READ
5. Read address 0F0 (hex) Valid READ
6. Read address 70F (hex) Initiate STORE
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles are used in the sequence, although it
is not necessary that G is LOW for the sequence to be
valid. After the t_STORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
1. Read address 000 (hex) Valid READ
2. Read address 555 (hex) Valid READ
3. Read address 2AA (hex) Valid READ
4. Read address 7FF (hex) Valid READ
5. Read address 0F0 (hex) Valid READ
6. Read address 70E (hex) Initiate RECALL
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
HSB Nonvolatile STORE
The hardware controlled STORE Busy pin (HSB) is
connected to an open drain circuit acting as both input
and output to perform two different functions. When
driven LOW by the internal chip circuitry it indicates that
a STORE operation (initiated via any means) is in pro-
gress within the chip. When driven LOW by external cir-
cuitry for longer than t_w(H)S, the chip will conditionally
initiate a STORE operation after t_dis(H)S.
READ and WRITE operations that are in progress
when HSB is driven LOW (either by internal or external
circuitry) will be allowed to complete before the STORE
operation is performed, in the following manner.
After HSB goes LOW, the part will continue normal
SRAM operation for t_dis(H)S. During t_dis(H)S, a transition
on any address or control signal will terminate SRAM
operation and cause the STORE to commence.
Note that if an SRAM WRITE is attempted after HSB
has been forced LOW, the WRITE will not occur and
the STORE operation will begin immediately. HARD-
WARE-STORE-BUSY (HSB) is a high speed, low drive
capability bidirectional control line.
In order to allow a bank of U632H16s to perform syn-
chronized STORE functions, the HSB pin from a num-
ber of chips may be connected together. Each chip
contains a small internal current source to pull HSB
HIGH when it is not being driven LOW. To decrease the
sensitivity of this signal to noise generated on the PC
board, it may optionally be pulled to power supply via
an external resistor with a value such that the combi-
ned load of the resistor and all parallel chip connections
does not exceed I_HSBOL at V_OL (see Figure 1 and 2).
Only if HSB is to be connected to external circuits, an
external pull-up resistor should be used.
During any STORE operation, regardless of how it was
initiated, the U632H16 will continue to drive the HSB
pin LOW, releasing it only when the STORE is com-
plete.
Upon completion of a STORE operation, the part will be
disabled until HSB actually goes HIGH.
Hardware Protection
The U632H16 offers hardware protection against inad-
vertent STORE operation during low voltage condi-
tions. When V_CAP < V_SWITCH, all software or HSB initia-
ted STORE operations will be inhibited.
Preventing Automatic STORES
The PowerStore function can be disabled on the fly by
holding HSB HIGH with a driver capable of sourcing
15 mA at V_OH of at least 2.2 V as it will have to over-
power the internal pull-down device that drives HSB
LOW at the onset of an PowerStore for 50 ns.
When the U632H16 is connected for PowerStore ope-
ration (see Figure 1) and V_CCX crosses V_SWITCH on the
way down, the U632H16 will attempt to pull HSB LOW;
if HSB does not actually get below V_IL, the part will stop
trying to pull HSB LOW and abort the PowerStore
attempt.
Disabling Automatic STORES
If the PowerStore function is not required, then V_CAP
should be tied directly to the power supply and V_CCX
should by tied to ground. In this mode, STORE opera-
tion may be triggered through software control or the
HSB pin. In either event, V_CAP (Pin 1) must always
have a proper bypass capacitor connected to it (Figure
2).
STK Control #ML0046 12
Rev 1.0
March 31, 2006