RT9238 Datasheet, PDF(12/24 Page) List of Unclassifed Manufacturers – VRM 8.5 PWM AND TRIPLE LINEAR POWER SYSTEM CONTROLLER

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RT9238 Datasheet, PDF (12/24 Pages) List of Unclassifed Manufacturers – VRM 8.5 PWM AND TRIPLE LINEAR POWER SYSTEM CONTROLLER

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RT9238

Preliminary

10V

3.0V

ATX12V

ATX5V

SS24

VTTPG

SS13

PGOOD

ATX3.3V

VOUT4 (1.8V)

VOUT1 (1.65V)

VOUT2 (1.2V)

VOUT3 (1.5V)

T0 T1 T2 T3 T4T5

TIME

Fig.3 Soft-start Interval

Fault Protection

All four outputs are monitored and protected against

extreme overload. The chipâs response to an output

overload is selective, depending on the faulting

output.

An over-voltage on VOUT1 output (FB1) disables

outputs 1, 2, and 3, and latches the IC off. An under-

voltage on VOUT4 output latches the IC off. A single

over-current event on output 1, or an under-voltage

event on output 2 or 3, increments the respective

fault counters and triggers a shutdown of outputs 1,

2, and 3, followed by a soft-start re-start. After three

consecutive fault events on either counter, the chip is

latched off. Removal of bias power resets both the

fault latch and the counters. Both counters are also

reset by a successful start-up of all the outputs.

Fig.3 shows a simplified schematic of the fault logic.

The over-current latches are set dependent upon the

states of the over-current (OC1), output 2 and 3

under-voltage (UV2, UV3) and the soft-start signals

(SS13, SS24). Window comparators monitor the SS

pins and indicate when the respective CSS pins are

fully charged to above 4.0V (UP signals). An under-

voltage on either linear output (VSEN2, VSEN3, or

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VSEN4) is ignored until the respective UP signal

goes high. This allows VOUT3 and VOUT4 to increase

without fault at start-up. Following an over-current

event (OC1, UV2, or UV3 event), bringing the SS24

pin below 0.8V resets the over-current latch and

generates a soft-started ramp-up of the outputs 1, 2,

and 3.

SS13UP

UV3

OC1

SS13

0.8V

SS24

UV4

UV2

LATCH

COUNTER

INHIBIT 1,2,3

SSDOWN

SS24UP

POR

LATCH

FAULT

LATCH

COUNTER

Q FAULT

Fig.4 Fault Logic-simplified Schematic

OUT1 Over-Voltage Protection

During operation, a short across the synchronous

PWM upper MOSFET (Q1) causes VOUT1 to

increase. When the output exceeds the over-voltage

threshold of 115% of DACOUT, the over-voltage

comparator trips to set the fault latch and turns the

lower MOSFET (Q2) on. This blows the input fuse

and reduces VOUT1.

A separate over-voltage circuit provides protection

during the initial application of power. For voltages on

the VCC pin below the power-on reset (and above

~4V), the output level is monitored for voltages above

1.3V. Should FB1 exceed this level, the lower

MOSFET, Q2, is driven on.

Over-Current Protection

All outputs are protected against excessive over-

currents. The PWM controller uses the upper

DS9238-01 July 2001

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