DEM16216SYH-LY Datasheet, PDF (12/22 Pages) List of Unclassifed Manufacturers – DEM16216SYH-LY

DEM 16216 SYH-LY
Product Specification
11) Read data to RAM
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read binary 8-bit data from DDRAM/CGRAM.
The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM is not
performed before this instruction, the data that is read first is invalid, because the direction of AC is not determined.
If you read RAM data several times without RAM address set instruction before read operation, you can get correct
RAM data. In the case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address
set instruction; it also transfers RAM data to the output data register.
After read operation the address counter is automatically increased/decreased by 1 according to the entry mode. After
CGRAM read operation, display shift may not be executed correctly.
In the case of RAM write operation, after this AC is increased/decreased by 1 like read operation. At his time, AC
indicates the next address position, but your can read only the previous data by the read instruction.
Table 5.instruction table
Instruction Code
Instruction
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB
1
DB0
Description
Execution
time
(fosc=
270kHz)
Clear
Display
00
0
0
0
0
0
0
0
Write “20H” to DDRAM and set
1 DDRAM address to “00H” from 1.53 ms
AC.
Return
Home
00
0
0
0
0
0
Set DDRAM address to “00H”from
0
1
x AC and return cursor to its original 1.53ms
position if shifted.
Entry Mode
set
0
0
0
0
0
0
0
1
I/D
SH
Assign cursor moving direction and
enable the shift of entire display.
39us
Display
Set display (D), cursor(C), and
ON/OFF 0 0
0
0
0
0
1
DC
B blinking of cursor (B) on/off control
39us
Control
bit.
Cursor or
Display shift
0
0
0
0
0
1 S/C R/L X
Set cursor moving and display shift
X control bit, and the direction without
changing of DDRAM data.
39us
Set interface data length (DL:4-
Function set 0 0
0
0
1 DL N
F
X
X
bit/8-bit), numbers of display line
(N:1-line/2-line, display font type
39us
(F:0…)
Set
CGRAM 0 0
address
0
1
AC5
AC4
AC3
AC2
AC
1
AC0
Set CGRAM address in address
counter.
39us
Set
CGRAM 0 0
address
1
AC6
AC5
AC4
AC3
AC2
AC
1
AC0
Set DDRAM address in address
counter.
39us
Read busy
flag and
0
address
1
Whether during internal operation or
BF
AC6
AC5
AC4
AC3
AC2
AC
1
AC0
not can be known by reading BF.
The contents of address counter can
also be read.
0us
Write data
to RAM
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal RAM
(DDRAM/CGRAM).
43us
Read data to
RAM
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data into internal RAM
(DDRAM/CGRAM).
43us
NOTE: when you make an MPU program with checking the busy flag (DB7), it must be necessary 1/2 Fosc for
executing the next instruction by falling E signal after the busy flag (DB7) goes to “0”.
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