PLI9080 Datasheet, PDF (119/133 Pages) List of Unclassifed Manufacturers – PCI I/O ACCELERATOR

SECTION 8
PCI 9080
TIMING DIAGRAMS
0ns
100ns
200ns
300ns
400ns
500ns
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LBE[3..0]#
LW/R#
LD[31..0]
LA[31:2]
DT/R#
DEN#
BTERM#
READYI#
<--- PCI9060 DRIVES BUS
PCI9060 FLOATS BUS -->
XXX1
0000, DOES NOT CHG, UNALIGNED HAS OWN CYCLE WITH ADS
D0
A[3:2]=11
A
D1
A[3:2]=00
A+4
D2
D3
D4
D5
01
10 A[3:2]=11 A[3:2]=00
A+8
A+12 A+16 A+20
D6
D7
D8
A+24 A+28 A+32
Note: Not all byte enables asserted or a quad boundary LA[3:2]=11 results in a new ADS#.
(no wait states, 32-bit bus, burst enabled, BTERM disabled)
Timing Diagram 8-14. (C Mode) PCI 9080 DMA or Direct Slave Burst Write, BTERM Disabled
600ns
©PLX Technology, Inc., 1997
Page 111
Version 0.93