SPHE8200A Datasheet, PDF (11/40 Pages) List of Unclassifed Manufacturers – DVD SINGLE CHIP MPEG A/V PROCESSOR

Preliminary
SPHE8200A
Signal
R_CS1_B/GPIO
Pin
State
Description
69
I/O
ROM / SRAM / flash chip select #1 (first device) or GPIO
tial ^{GY R_CS2_B/GPIO}
nfidenNOLOINC _{R_CS3_B/GPIO}
nplus ^{ICCoTEACNHDINSLEY} CLKIN
u ^{N CLKOUT}
S N _CH ^O _{M_DD[7]}
U _R ^{E M_DD[6]}
S _E ^{S M_DD[5]}
M_DD[4]
r ^U M_DD[3]
o ^{M M_DD[2]}
F _& ^M_DD[1]
Priority selection
sft_cfg1[0]=1’b1
(other)
Function
R_CS1_B (default)
GPIO[13]
70
I/O
ROM / SRAM / flash chip select #2 or GPIO
Priority selection
sft_cfg1[1]=1’b1
sft_cfg4[8:6]=3’b100
(other)
Function
R_CS2_B (default)
DSP FL2
GPIO[35]
71
I/O
ROM / SRAM / flash chip select #3 or GPIO
Priority selection
sft_cfg1[2]=1’b1
sft_cfg4[11:9]=3’b100
(other)
Function
R_CS3_B (default)
DSP FLAGOUT
GPIO[36]
Crystal / Clock Pins (2)
78
I
Clock input / crystal in (XTALI)
77
O
Clock output / crystal out (XTALO)
SDRAM Interface Pins (57)
80
I/O
SDRAM data bus [7]
81
I/O
SDRAM data bus [6]
82
I/O
SDRAM data bus [5]
83
I/O
SDRAM data bus [4]
84
I/O
SDRAM data bus [3]
86
I/O
SDRAM data bus [2]
87
I/O
SDRAM data bus [1]
M_DD[0]
88
I/O
SDRAM data bus [0]
M_WE_B
89
O
SDRAM write enable / row precharge
M_CAS_B
91
O
SDRAM column address strobe
M_RAS_B
92
O
SDRAM row address strobe / precharge
M_CS_B
93
O
SDRAM chip select
M_BA0
94
O
SDRAM bank select address [0]
M_DD[15]
96
I/O
SDRAM data bus [15]
M_DD[14]
97
I/O
SDRAM data bus [14]
M_DD[13]
98
I/O
SDRAM data bus [13]
M_DD[12]
99
I/O
SDRAM data bus [12]
M_DD[11]
101
I/O
SDRAM data bus [11]
© Sunplus Technology Co., Ltd.
11
Proprietary & Confidential
OCT. 07, 2003
Preliminary Version: 0.2