MC740-430E Datasheet, PDF (11/15 Pages) List of Unclassifed Manufacturers – 47-Gb/s 4:1 Multiplexer

NEL
MC740-430E
Step 1 CLK10 output
Insert a phase shifter between CLK10 output terminal and the PPG. Phase shift
range of the phase shifter should be 100 ps_pp.
Observe the 20 Gb/s monitor outputs by using the oscilloscope. If the CLK10 delay
is not optimum, the monitor outputs will be similar to Fig. 6(a). Adjust the CLK10
delay until the monitor output becomes clear (see Fig. 6(b)). When the 20G
monitor outputs become clear, the 40G monitor output automatically becomes clear.
20Gb/s odd
500 mV/div
20Gb/s even
500 mV/div
40Gb/s
150 mV/div
20Gb/s odd
500 mV/div
(a) with an unsuitable delay
20 psV/div
20Gb/s even
500 mV/div
40Gb/s
150 mV/div
Fig. 6.
20 psV/div
(b) after delay adjustment
20G and 40G monitor output waveforms.
Informally, similar adjustment could be done by shifting the delay of CLK10 input
(clock delay time from PPG). The output timing from the latching stage, or input
data timing for the 4:1 MUX, can be controlled by CLK10 input as shown in Fig. 7.
However, this method cannot be applicable for all situations because the clock phase
margin of the latching stage is smaller than 360 degree.
DATA 3, 2, 1, 0
4
CLK10 input
latched data
Latching
4
stage
4:1
MUX
internal clock
Fig. 7. Delay adjustment by CLK10 input.
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