HWD2111 Datasheet, PDF (11/19 Pages) List of Unclassifed Manufacturers – Dual 105mW Headphone Amplifier with Digital Volume Control and Shutdown Mode

Typical Performance Characteristics (Continued)
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Frequency Response
Supply Current vs
Supply Voltage
Application Information
DIGITAL VOLUME CONTROL
The HWD2111’s gain is controlled by the signals applied to the
CLOCK and UP/DN inputs. An external clock is required to
drive the CLOCK pin. At each rising edge of the clock signal,
the gain will either increase or decrease by a 3dB step
depending on the logic voltage level applied to the UP/DN
pin. A logic high voltage level applied to the UP/DN pin
causes the gain to increase by 3dB at each rising edge of the
clock signal. Conversely, a logic low voltage level applied to
the UP/DN pin causes the gain to decrease 3dB at each
rising edge of the clock signal. For both the CLOCK and
UP/DN inputs, the trigger point is 1.4V minimum for a logic
high level, and 0.4V maximum for a logic low level.
There are 16 discrete gain settings ranging from +12dB
maximum to −33dB minimum. Upon device power on, the
amplifier’s gain is set to a default value of 0dB. However,
when coming out of shutdown mode, the HWD2111 will revert
back to its previous gain setting.
The HWD2111’s CLOCK and UP/DN pins should be de-
bounced in order to avoid unwanted state changes during
transitions between V_IL and V_IH. This will ensure correct
operation of the digital volume control. A microcontroller or
microprocessor output is recommended to drive the CLOCK
and UP/DN pins.
FIGURE 2. Timing Diagram
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