HV7131R Datasheet, PDF (11/33 Pages) List of Unclassifed Manufacturers – CMOS Image Sensor

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HV7131R
Register Description
Register
Device ID
Sensor Control A
Sensor Control B
Output Inversion
Row Start Add Upper
Row Start Add Lower
Col. Start Add Upper
Col. Start Add Lower
Window Height Upper
Window Height Lower
Window Width Upper
Window Width Lower
HBLANK Time Upper
HBLANK Time Lower
VBLANK Time Upper
VBLANK Time Lower
Integration Time High
Integration
Time
Middle
Integration Time Low
Pre-amp Gain
Red Color Gain
Green Color Gain
Blue Color Gain
Analog Bias Control A
Analog Bias Control B
Black Level Threshold
Initial ADC Offset Red
Initial ADC Offset
Green
Initial ADC Offset Blue
Symbol
DEVID
SCTRA
SCTRB
OUTIV
RSAU
RSAL
CSAU
CSAL
WIHU
WIHL
WIWU
WIWL
HBLU
HBLL
VBLU
VBLL
INTH
INTM
INTL
PAG
RCG
GCG
BCG
ACTRA
ACTRB
BLCTH
ORedI
OGrnI
OBluI
Address
00h
01h
02h
03h
10h
11h
12h
13h
14h
15h
16h
17h
20h
21h
22h
23h
25h
Default
02h
09h
01h
00h
00h
02h
00h
02h
01h
e2h
02h
82h
00h
d0h
00h
08h
06h
Description
Product Identification, Revision
Number.
ClkDiv[6:4], ABLCEn[3], PxlVs[2],
XFlip[1], YFlip[0]
VCLK Disable[6], ADCPwDn[5], Black
Mode[4], Sleep[3], VsHsEn[2],
BLDataEn[1], StrobeEn[0]
ByrDpcEn[6],
ByrDpcTh[5:4],
ClkHSC[3], InvVSC[2], InvHSC[1],
InvVCLK[0]
Row Start Address Upper Byte[8]
Row Start Address Lower Byte[7:0]
Column Start Address Upper Byte[9:8]
Column Start Address Lower Byte[7:0]
Window Height Upper Byte[8]
Window Height Lower Byte[7:0]
Window Width Upper Byte[9:8]
Window Width Lower Byte[7:0]
HBLANK Time Upper Byte[15:8].
HBLANK Time Lower Byte[7:0].
VBLANK Time Upper Byte[15:8].
VBLANK Time Lower Byte[7:0].
Integration Time [23:16]
26h 5Bh Integration Time [15:8]
27h 9ah Integration Time [7:0]
30h
10h
Gain for Pre-amp (0.5~16.5 times with
8bit resolution) [7:0]
31h
10h
Gain for Red Pixel Read-out (0.5~2
times with 6bit resolution) [5:0]
32h
10h
Gain for Green Pixel Read-out (0.5~2
times with 6bit resolution [5:0]
33h
10h
Gain for Blue Pixel Read-out (0.5~2
times with 6bit resolution [5:0]
34h 17h CDS Bias [6:4], PGA Bias [3:0]
35h
7fh Reset Clamp [7:4], ADC Bias [3:0]
40h
ffh
Auto Black Level Pixel Threshold
Value
41h
7fh Initial ADC Offset Red
42h
7fh Initial ADC Offset Green
43h
7fh Initial ADC Offset Blue
This document is a general product description and is subject to change without notice. MagnaChip
Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent
licenses are implied.
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2004 MagnaChip Semiconductor Ltd.