DM562P Datasheet, PDF (11/43 Pages) List of Unclassifed Manufacturers – V.90 Intergrated Data/Fax/Voice/Speakephone Modem Device Single Chip with Memory Built in

DM562P
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
PCI Subsystem Vender ID Low Byte Data Port:
Address F804H (pci only)
Write only
This port configures PCI Subsystem Vender ID low
byte. (Offset 2C of PCI configuration register space)
PCI Subsystem Vender ID High Byte Data Port:
Address F805H (pci only)
Write only
This port configures PCI Subsystem Vender ID high
byte. (Offset 2D of PCI configuration register space)
PCI Subsystem Device ID Low Byte Data Port:
Address F806H
Write only
This port configures PCI Subsystem Device ID low
byte. (Offset 2E of PCI configuration register
space)
PCI Subsystem Device ID High Byte Data Port:
Address F807H
Write only
This port configures PCI Subsystem Device ID low
byte. (Offset 2F of PCI configuration register
space)
PCI Power Management New Capability:
Address F808H, Bit 4 (pci only)
Write only
This bit configures if support PCI Power
Management. (Offset 06 bit 4 of PCI configuration
register space)
PCI Power Management Power State:
Address F809H, Bit[1..0] (pci only)
Write / Read
These bits configures PCI Power management
Power State. (Offset 54 bit [1..0] of PCI
configuration register space)
PCI Power Management PME_STATUS:
Address F80AH, Bit 1
Write only
This bit configures PCI Power status. (Offset 55 bit
7 of PCI configuration register space)
PCI Power Management PME_EN:
Preliminary
Version: DM562P-DS-P02
February 28, 2001
Address F80AH, Bit 0
Write only
This bit configures PCI if enable PME wake up
(Offset 55 bit 0 of PCI configuration register space)
PCI PME_D3_Support:
Address F80BH, Bit 0
Write only
This port configures PCI if support PME wake up at
D3 state. (Offset 53 bit [8..7] of PCI configuration
register space)
HDLC RxDataBits Register: Address DC00H
Write only
Once the RxDataBit set to 1, the data in the
RxBuffer will be transferred to RxFIFO. The
transfer bit number is the same as the programming
value of RxDataBits Register.
HDLC RxBuffer: Address DC01H
Write only
Receive data will be written to the RxBuffer and will
be input to the RxHDLC circuit. The RxBuffer is 16
bytes wide.
HDLC RxFiFo: Address DC01H
Read only
After the data has been passed from the RxBuffer to
the RxHDLC circuit, the RxHDLC circuit will remove
the 7eH patterns and transfer the results to the
RxFIFO. There RxFIFO is 21 bytes wide.
HDLC TxDataBits Register: Address DC02H
Write only
Data written to TxDataBits will be presented to the
TxFIFO. The data in TxFIFO will be transferred to
TXHDLC circuit. The transfer bit number is the same
as the value of TxDataBits register. If the TxFIFO is
empty , a 7e pattern will be loaded to the TxFIFO. If
TxFIFO is not empty and the data frame has the
pattern of five consecutive “1” , then the TXHDLC
circuit will insert “0” automatically.
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