CMI8768 Datasheet, PDF (11/17 Pages) C-Media Electronics – PCI 8CH Integrated Sound Chip

5. Pin Description
PCI 8CH Integrated Sound Chip
CMI8768 Datasheet Rev 0.9
5.1 Digital I/O
Pin No
1-2,
5-7,
12-16,
19-21,
32-35,
38-41,
43-44,
47-52,
126-128
117
119
120
121
122
9
23
24
25
26
29
30
8, 22,
31, 42
88
89
55
56
87
84
85
112
98
86
113
Signal Name Type
Description
XA31 – XA0
I/O PCI bus address and data lines
XINTA
XPRST
XCLK33
XGNT
XREQ
XIDSEL
XFRAME
XIRDY
XTRDY
XDEVSEL
XSTOP
XPAR
XCBE0
XCBE3
XTXD
XRXD
XIN
XOUT
XGBIO0
XEECS
XMBCSZ
ZVCLK
XSPDIFO
XSPDIFI
XSPDIFI2
O Interrupt request, active-low
I Reset
I PCI bus clock
I Bus master grant, active-low.
O Bus master request, tri-state output, active-low.
I ID select, active-high.
I/O Cycle frame, active-low.
I/O
Initiator ready, active-low. The bus master
device is ready to transmit or receive data.
I/O
Target ready, active-low. The target device is
ready to transmit or receive data.
Device select, active-low. The target device has
I/O decoded the address of the current transaction
as its own chip select range.
Stop transaction, active-low. The target device
I/O request to the master to stop the current
transaction.
Parity. The pin indicates even parity across
I/O XA31-XA9 and XCBE3-XCBE0 for both address
and data phases.
–
I/O
Multiplexed command / byte enable. These pins
indicate cycle type during the address phase of a
transaction.
O MIDI transmit data
I MIDI receive data
I 14.318 MHz crystal input or ext. oscillator input
O 13.318 MHz crystal output or NC
I/O General purpose I/O
O EEPROM chip select
I Audio chip enable select (low:enable)
I ZV port clock
O S/PDIF output
I
S/PDIF input 1 /
ZV port LR channel clock
I
S/PDIF input 2 (TTL 5V) /
ZV port data input
Copyright 2003-2004 © C-Media Electronics Inc.
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