SA25C1024 Datasheet, PDF (10/19 Pages) List of Unclassifed Manufacturers – 1Mb EEPROM SPI with 10MHz and Low Standby

Functional Description
Figure 4 presents a schematic diagram of
the SPI serial interface.
MASTER:
MICROCONTROLLER
DATA OUT
DATA IN
SERIAL CLOCK
SSO
SS1
SS2
SS3
SLAVE:
SA25C1024
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
Figure 4. SPI Serial Interface
The SA25C1024's SPI consists of an 8-bit
instruction register that decodes a specific
instruction to be executed. Six different
instructions (called opcodes) are
incorporated in the device for various
operations. Table 5 lists the instructions set
and the format for proper operation. All
opcodes, array addresses and data are
transferred in an MSB-first-LSB-last
fashion. Detailed information about each of
these opcodes is provided under individual
instruction descriptions in the sections that
follow.
SA25C1024 Data Sheet
SAIFUN
10
Table 5. Instruction Set
Instruction Instruction
Name
Format
Operation
WREN
WRDI
RDSR
WRSR
READ
WRITE
0000X110
0000X100
0000X101
0000X001
0000X011
0000X010
Set Write Enable Latch
Reset Write Enable
Latch
Read Status Register
Write Status Register
Read Data from
Memory Array
Write Data to Memory
Array
In addition to the instruction register, the
device also contains an 8-bit status register
that can be accessed by RDSR and WRSR
instructions. The byte defines the Block
Write Protection (BP1 and BP0) levels,
Write Enable (WEN) status, Busy/Rdy
(/RDY) status and Hardware Write Protect
(WPBEN) status of the device. Table 6
illustrates the format of the status register.
Table 6. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0
WPBEN X X X BP1 BP0 WEN /RDY
Write Enable (WREN)
The device powers up in the Write Disable
state when V_CC is applied. All programming
instructions must be preceded by a WREN
instruction.
Write Disable (WRDI)
To protect the device against inadvertent
writes, the WRDI instruction disables all
programming modes. The WRDI
instruction is independent of the WP pin's
status.