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FM25L16 Datasheet, PDF (10/14 Pages) List of Unclassifed Manufacturers – 16Kb FRAM Serial 3V Memory
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FM25L16
AC Parameters (TA = -40° C to + 85° C, CL = 30pF)
VDD 2.7 to 3.0V
Symbol
Parameter
Min
Max
fCK
SCK Clock Frequency
0
18
tCH
Clock High Time
25
tCL
Clock Low Time
25
tCSU
Chip Select Setup
10
tCSH
Chip Select Hold
10
tOD
Output Disable Time
20
tODV
Output Data Valid Time
25
tOH
Output Hold Time
0
tD
Deselect Time
60
tR
Data In Rise Time
50
tF
Data In Fall Time
50
tSU
Data Setup Time
5
tH
Data Hold Time
5
tHS
/Hold Setup Time
10
tHH
/Hold Hold Time
10
tHZ
/Hold Low to Hi-Z
20
tLZ
/Hold High to Data Active
20
Notes
1. tCH + tCL = 1/fCK.
2. Characterized but not 100% tested in production.
3. Rise and fall times measured between 10% and 90% of waveform.
VDD 3.0 to 3.6V
Min
Max
0
20
22
22
10
10
20
20
0
60
50
50
5
5
10
10
20
20
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
2
1,3
1,3
2
2
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V)
Symbol
Parameter
tPU
Power Up (VDD min) to First Access (/CS low)
tPD
Last Access (/CS high) to Power Down (VDD min)
tVR
VDD Rise Time
tVF
VDD Fall Time
Min Max Units Notes
1
-
ms
0
-
µs
50
-
µs/V
1,2
100
-
µs/V
1,2
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V)
Symbol
Parameter
CO
Output Capacitance (SO)
CI
Input Capacitance
Notes
1. This parameter is periodically sampled and not 100% tested.
2. Slope measured at any point on VDD waveform.
Min
Max
Units Notes
-
8
pF
1
-
6
pF
1
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
Output Load Capacitance
10% and 90% of VDD
5 ns
0.5 VDD
30 pF
Rev. 2.0
Mar. 2005
Page 10 of 14
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