WS512K32-15G1 Datasheet, PDF (1/11 Pages) List of Unclassifed Manufacturers – 512K X 32 SRAM MODULE SMD 5962-94611

WS512K32-XXX
512Kx32 SRAM MODULE, SMD 5962-94611
FEATURES
n Access Times of 15*, 17, 20, 25, 35, 45, 55ns
n Packaging
• 66 pin, PGA Type, 1.075" square, Hermetic Ceramic HIP
(Package 400).
• 68 lead, 40mm Hermetic Low Profile CQFP, 3.5mm (0.140")
(Package 502)¹, Package to be developed.
• 68 lead, Hermetic CQFP (G2T)¹, 22.4mm (0.880") square
(Package 509) 4.57mm (0.180") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3).
• 68 lead, Hermetic CQFP (G1U), 23.9mm (0.940") square
(Package 519) 3.57mm (0.140") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3).
• 68 lead, Hermetic CQFP (G1U), 23.9mm (0.940") square
(Package 524) 4.06mm (0.160") height.
n Organized as 512Kx32, User Configurable as 1Mx16 or 2Mx8
n Commercial, Industrial and Military Temperature Ranges
n TTL Compatible Inputs and Outputs
n 5 Volt Power Supply
n Low Power CMOS
n Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
n Weight
WS512K32-XH1X - 13 grams typical
WS512K32-XG2TX¹ - 8 grams typical
WS512K32-XG1UX - 5 grams typical
WS512K32-XG1TX - 5 grams typical
WS512K32-XG4TX¹ - 20 grams typical
* 15ns Access Time available only in Commercial and Industrial Temperature.
This speed is not fully characterized and is subject to change without notice.
Note 1: Package Not Recommended For New Design
FIG. 1 PIN CONFIGURATION FOR WS512K32N-XH1X
TOP VIEW
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-18 Address Inputs
WE1-4 Write Enables
CS1-4
Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
NC
Not Connected
BLOCK DIAGRAM
November 2001 Rev. 9
1
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