WS128K32V Datasheet, PDF (1/8 Pages) List of Unclassifed Manufacturers – 128Kx32 3.3V SRAM MULTICHIP PACKAGE

WS128K32V-XXX
128Kx32 3.3V SRAM MULTICHIP PACKAGE PRELIMINARY*
FEATURES
s Access Times of 15**, 17, 20, 25, 35ns
s 3.3 Volt Power Supply
s Low Voltage Operation
s Low Power CMOS
s Packaging
s TTL Compatible Inputs and Outputs
• 66-pin, PGA Type, 1.075 inch square Hermetic Ceramic
HIP (Package 400)
• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880 inch) square
(Package 509), 4.57mm (0.180 inch) high. Designed to fit
JEDEC 68 lead 0.990" CQFJ footprint (Fig. 2)
• 68 lead, Hermetic CQFP (G1U), 23.8mm (0.940 inch)
square (Package 509), 3.56mm (0.140 inch) high.
s Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s Weight
WS128K32V-XG2TX - 8 grams typical
WS128K32V-XG1UX - 5 grams typical
WS128K32V-XH1X - 13 grams typical
s Organized as 128Kx32; User Configurable as 256Kx16 or
512Kx8
s Commercial, Industrial and Military Temperature Ranges
* This data sheet describes a product that is not fully qualified or
characterized and is subject ot change without notice.
** Commercial and Industrial temperature ranges only.
4
FIG. 1 PIN CONFIGURATION FOR WS128K32NV-XH1X
TOP VIEW
PIN DESCRIPTION
1
12
23
I/O8
WE2
I/O15
I/O9
CS2
I/O14
I/O10
GND
I/O13
A13
I/O11
I/O12
A14
A10
OE
A15
A11
NC
A16
A12
WE1
NC
VCC
I/O7
I/O0
CS1
I/O6
I/O1
NC
I/O5
34
45
56
I/O24
VCC
I/O31
I/O25
CS4
I/O30
I/O26
WE4
I/O29
A6
I/O27
I/O28
A7
A3
A0
NC
A4
A1
A8
A5
A2
A9
WE3
I/O23
I/O16
CS3
I/O22
I/O17 GND
I/O21
I/O0-31
A0-16
WE1-4
CS1-4
OE
VCC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
OE
A0-16
W E1C S 1
W E2 C S2
W E3 C S 3
W E 4C S4
128K x 8
128K x 8
128K x 8
128K x 8
I/O2
I/O3
I/O4
11
22
33
I/O18
I/O19
I/O20
44
55
66
8
I/O0-7
8
I/O8-15
8
I/O16-23
8
I/O24-31
April 2001 Rev. 2
1
White Microelectronics • [phone] • www.whiteedc.com