UT6264C Datasheet, PDF (1/10 Pages) List of Unclassifed Manufacturers – 8K X 8 BIT LOW POWER CMOS SRAM


UTRON
Rev. 1.1
FEATURES
Access time : 35/70ns (max.)
Low power consumption :
Operating : 45/30 mA (typ.)
CMOS Standby : 2mA (typ.) normal
2 µA (typ.) L-version
1 µA (typ.) LL-version
Single 4.5V~5.5V power supply
Operating temperature :
Commercial : 0℃~70℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
FUNCTIONAL BLOCK DIAGRAM
A0-A12
Vcc
Vss
DECODER
8K × 8
MEMORY
ARRAY
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE1
CE2
OE
WE
CONTROL
CIRCUIT
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
The UT6264C is a 65,536-bit low power CMOS
static random access memory organized as 8,192
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
Easy memory expansion is provided by using two
chip enable input.( _{CE 1} ,CE2) ,and supports low
data retention voltage for battery back-up
operation with low data retention current.
The UT6264C operates from a single 4.5V~5.5V
power supply and all inputs and outputs are fully
TTL compatible.
PIN CONFIGURATION
NC
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
I/O1
11
I/O2
12
I/O3
13
Vss
14
28
Vcc
27
WE
26
CE2
25
A8
24
A9
23
A11
22
OE
21
A10
20
CE1
19
I/O8
18
I/O7
17
I/O6
16
I/O5
15
I/O4
PDIP/SOP
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A12
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE1 ^,CE2
Chip Enable Inputs
WE
Write Enable Input
OE
Output Enable Input
V_CC
Power Supply
V_SS
Ground
NC
No connection
GENERAL DESCRIPTION
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]
1
P80028