UT1553 Datasheet, PDF (1/61 Pages) List of Unclassifed Manufacturers – BCRTM

UT1553 BCRTM
FEATURES
p Comprehensive MIL-STD-1553 dual-redundant Bus
Controller (BC) and Remote Terminal (RT) and
Monitor (M) functions
p MIL-STD-1773 compatible
p Multiple message processing capability in BC
p Time tagging and message logging in RT and M modes
p Automatic polling and intermessage delay in
BC mode
p Programmable interrupt scheme and internally
generated interrupt history list
p Register-oriented architecture to enhance
programmability
p DMA memory interface with 64K addressability
p Internal self-test
p Radiation-hardened option available for 84-lead
flatpack package only
p RemoteterminaloperationsinASD/ENASD-certified
(SEAFAC)
p Available in 84-pin pingrid array, 84-lead flatpack, 84-
lead leadless chip-carrier
p Standard Microcircuit Drawing 5962-89577 available
- QML Q and V compliant
1553
DATA
CHANNEL
A
1553
DATA
CHANNEL
B
TIMERON
12MHz
MASTER
RESET
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
CLOCK &
RESET
LOGIC
INTERRUPT
HANDLER
DUAL
CHANNEL
ENCODER/
DECODER
MODULE
PARALLEL-
TO-SERIAL
CONVER-
SION
SERIAL-TO-
PARALLEL
CONVER-
SION
BC PROTOCOL
&
MESSAGE
HANDLER
16
BUS
TRANSFER
LOGIC
RT/MONITOR
PROTOCOL &
MESSAGE
HANDLER
16
TIMEOUT
ADDRESS
GENERATOR
DMA/CPU
16
CONTROL
16
16
16
BUILT-
IN-
TEST
DMA ARBITRATION
REGISTER CONTROL
DUAL-PORT MEMORY CONTROL
ADDRESS
Figure 1. BCRTM Block Diagram
REGISTERS
CONTROL
STATUS
CURRENT BC (or M) BLOCK/
RT DESCRIPTOR SPACE
POLLING COMPARE
BUILT-IN-TEST WORD
CURRENT COMMAND
INTERRUPT LOG
LIST POINTER
HIGH-PRIORITY
INTERRUPT ENABLE
HIGH-PRIORITY
INTERRUPT STATUS
STANDARD INTERRUPT
ENABLE
RT ADDRESS
BUILT-IN-TEST
START COMMAND
RESET COMMAND
RT TIMER
RESET COMMAND
MONITOR ADDRESS
CONTROL
MONITOR ADDRESS
SELECT (0-15)
MONITOR ADDRESS
SELECT (16-31)
16
16
DATA
BCRTM-1