U62256 Datasheet, PDF (1/9 Pages) List of Unclassifed Manufacturers – STANDARD 32K X 8 SRAM

U62256
Standard 32K x 8 SRAM
Features
Description
F 32768x8 bit static CMOS RAM
F Access times 70 ns, 100 ns
F Common data inputs and
data outputs
F Three-state outputs
F Typ. operating supply current
70 ns: 50 mA
100 ns: 40 mA
F TTL/CMOS-compatible
F Automatical reduction of power
dissipation in long Read Cycles
F Power supply voltage 5 V ⁺ 10 %
F Operating temperature ranges
0 to 70 °C
-40 to 85 °C
F CECC 90000 Quality Standard
F ESD protection > 2000 V
(MIL STD 883C M3015.7)
F Latch-up immunity >100 mA
F Package: SOP28 (330 mil)
The U62256 is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
MIXMOS cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new information
read is available. The data outputs
have not preferred state.
The Read cycle is finished by the
falling edge of W, or by the rising
edge of E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
Pin Configuration
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
22
SOP
8
21
9
20
10
19
11
18
12
17
13
16
14
15
Top View
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
November 01, 2001
Pin Description
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
1