SY10ELT23 Datasheet, PDF (1/4 Pages) Micrel Semiconductor – DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR

SY N ER GY
SEMICONDUCTOR
DUAL DIFFERENTIAL
PECL-to-TTL TRANSLATOR
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SY10ELT23
SY100ELT23
FEATURES
s 3.0ns typical propagation delay
s <500ps typical output-to-output skew
s Differential PECL outputs
s 24mA TTL outputs
s Flow-through pinouts
s ESD protection of 2000V
s Available in 8-pin SOIC package
DESCRIPTION
The SY10/100ELT23 are dual differential PECL-to-TTL
translators. Because PECL (Positive ECL) levels are
used, only +5V and ground are required. The small
outline 8-lead SOIC package and the low skew, dual
gate design of the ELT23 makes it ideal for applications
which require the tranlation of a clock and a data signal.
The ELT23 is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN CONFIGURATION/BLOCK DIAGRAM
D0 1
D0 2
PECL
D1 3
D1 4
8 VCC
7 Q0
TTL
6 Q1
5 GND
SOIC
TOP VIEW
PIN NAMES
Pin
Qn
Dn
VCC
GND
Function
TTL Outputs
Differential PECL Inputs
+5.0V Supply
Ground
© 1998 Synergy Semiconductor Corporation
5-232
Rev.: F Amendment: /0
Issue Date: August, 1998