STP2230SOP Datasheet, PDF (1/16 Pages) List of Unclassifed Manufacturers – Crossbar Switch

DATA SHEET
STP2230SOP
July 1997
XB1
Crossbar Switch
DESCRIPTION
The STP2230SOP crossbar switch ^[1] acts as the bridge among three UltraSPARC UPA devices. One of
the buses is dedicated to interfacing to system memory, while the other two are general-purpose
buses. These buses are used for interfacing memory, a processor bus, and an I/O bus. In this partic-
ular configuration, eighteen XB1s are required per system implementation.
FEATURES
• Three-port crossbar
- 16-bit data
- 8-bit processor
- 4-bit data ports
• Decoupled memory port; loading and unloading of memory data can take place in parallel with other operations
• Burst transfers operate on four bytes of data per slice
• Power-up safe buses; all buses power up tristated so there will be no bus contention with other parts which may
be on the buses
• Implemented in 0.8-micron BiCMOS and housed in a 48-pin TSSOP package (also called DGG or “shrink-wide
bus”)
1. The STP2230SOP crossbar switch is also referred to as BMX.
1