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| STK14C88 Datasheet, PDF (1/13 Pages) List of Unclassifed Manufacturers – 32K x 8 AutoStore nvSRAM QuantumTrap CMOS Nonvolatile Static RAM | |||
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STK14C88
32K x 8 AutoStore⢠nvSRAM
QuantumTrap⢠CMOS
Nonvolatile Static RAM
FEATURES
⢠25ns, 35ns and 45ns Access Times
⢠âHands-offâ Automatic STORE with External
68µF Capacitor on Power Down
⢠STORE to nonvolatile elements Initiated by
Hardware, Software or AutoStoreâ¢
⢠RECALL to SRAM Initiated by Software or
Power Restore
⢠10mA Typical ICC at 200ns Cycle Time
⢠Unlimited READ, WRITE and RECALL Cycles
⢠1,000,000 STORE Cycles to nonvolatile ele-
ments (Commercial/Industrial)
⢠100-Year Data Retention in nonvolatile ele-
ments (Commercial/Industrial)
⢠Single 5V + 10% Operation
⢠Commercial, Industrial and Military Tempera-
tures
⢠32-Pin SOIC, DIP and LCC Packages
DESCRIPTION
The Simtek STK14C88 is a fast static RAM with a
nonvolatile element incorporated in each static
memory cell. The SRAM can be read and written an
unlimited number of times, while independent, non-
volatile data resides in the nonvolatile elements.
Data transfers from the SRAM to the nonvolatile ele-
ments (the STORE operation) can take place auto-
matically on power down. A 68µF or larger capacitor
tied from VCAP to ground guarantees the STORE
operation, regardless of power-down slew rate or
loss of power from âhot swappingâ. Transfers from
the nonvolatile elements to the SRAM (the RECALL
operation) take place automatically on restoration of
power. Initiation of STORE and RECALL cycles can
also be software controlled by entering specific read
sequences. A hardware STORE may be initiated with
the HSB pin.
BLOCK DIAGRAM
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Quantum Trap
512 x 512
STATIC RAM
ARRAY
512 x 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCCX VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
PIN CONFIGURATIONS
HSB
32 - LCC
VCAP
A14
A12
A7
A6
A5
A4
A3
NC
A2
A1
A0
DQ0
DQ1
DQ2
VSS
A0 - A13
PIN NAMES
1
32 VCCX
2
31 HSB
3
30 W
4
29 A13
5
28 A8
6
27 A9
7
26 A11
8
25 G
9
24 NC
10
23 A10
11
22 E
12
21 DQ7
13
20 DQ6
14
19 DQ5
15
18 DQ4
16
17 DQ3
32 - DIP
32 - SOIC
A0 - A14
DQ0 -DQ7
E
Address Inputs
Data In/Out
Chip Enable
W
G
G
Write Enable
Output Enable
HSB
E
W
VCCX
VCAP
VSS
Hardware Store Busy (I/O)
Power (+ 5V)
Capacitor
Ground
December 2002
1 Document Control # ML0014 rev 0.0
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