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ST2202 Datasheet, PDF (1/65 Pages) List of Unclassifed Manufacturers – 8 BIT Integrated Microcontroller with 256K Bytes ROM | |||
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ST
Sitronix
ST2202
PRELIMINARY
8 BIT Integrated Microcontroller with 256K Bytes ROM
Notice: This is not a final specification. Some parameters are subject to change.
1. FEATURES
 Totally static 8-bit CPU
 ROM: 256K x 8-bit
 RAM: 4K x 8-bit
 Stack: Up to 128-level deep
 Operation voltage: 2.4V ~ 5.5V
 Operation frequency:
â 3.0Mhz@2.4V(Min.)
â 4.0Mhz@2.7V(Min.)
 Low Voltage Detector (LVD)
 Memory interface to ROM, RAM, Flash
 Memory configuration
â Three kinds of bank for program, data and interrupts
â 12-bit bank register supports up to 44M bytes
â 6 programmable chip-selects with 4 modes
â Maximum single device of 16M bytes at CS5
 General-Purpose I/O (GPIO) ports
â 48 multiplexed CMOS bidirectional bit programmable
I/Os
â Hardware de-bounce option for Port-A
â Bit programmable pull-up for input pins
â Bit programmable pull-up/down and open-drain/CMOS
for Port-C
 Programmable Watchdog Timer (WDT)
 Timer/Counter
â Two 8-bit timer, one can be a 16-bit event counter
â One 8-bit Base timer with 5 coexistent interrupt time
settings
 Three clocking outputs
â Clock sources including Timer0/1, baud rate generator
 11 prioritized interrupts with dedicated exception
vectors
â External interrupt (edge triggered)
â TIMER0 interrupt
â TIMER1 interrupt
â BASE timer interrupt
â PORTA interrupt (transition triggered)
â DAC reload interrupt
â LCD frame interrupt
â SPI interrupts (x2)
â UART interrupts (x2)
 Dual clock sources with warm-up timer
â Low frequency crystal oscillator (OSCX)
····················································32768 Hz
â RC oscillator (OSC) ······························· 500K ~ 4M Hz
â High frequency crystal/resonator oscillator
(Bonding option)······ 455K~4M Hz
 Direct Memory Access (DMA)
â Block-to-Block transfer
â Block to Single port
 LCD Controller (LCDC)
â Software programmable screen size up to 240X120
(including 160x160, 160x80, etc.)
â Support 1-, 4-bit LCD data bus
â Share system memory with display memory
â Unique internal bus for memory sharing with no loss of
the CPU time
â Diverse functions including virtual screen , panning ,
scrolling , contrast control and alternating signal
generator
â Support software 16 gray levels
 Universal Asynchronous Receiver/Transmitter (UART)
â Full-duplex operation
â Baud rate generator with one digital PLL
â Standard baud rates of 600 bps to 115.2 kbps
â Direct glueless support of IrDA physical layer protocol
â Two sets of I/Os (TX,RX) for two independent devices
 Serial Peripheral Interface (SPI)
â Master and slave modes
â 5 serial signals including enable and data-ready
â One stage buffer for transmitter and receiver for
continuous data exchange
â Programmable data length from 7-bit to 16-bit
 Programmable Sound Generator (PSG)
â Two channels with three playing modes
â Tone/noise generator
â 16-level volume control
â 8-bit PWM DAC for speech/voice
â Two dedicated outputs for directly driving and large
current
 Three power down modes
â WAI0 mode
â WAI1 mode
â STP mode
Ver 2.0a
1/65
2003-May-05
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