English
Language : 

SPT2210 Datasheet, PDF (1/22 Pages) List of Unclassifed Manufacturers – Y/C VIDEO ENCODER
SPT
SIGNAL PROCESSING TECHNOLOGIES
SPT2210
Y/C VIDEO ENCODER
FEATURES
• Supports NTSC (M) and PAL (B, D, G, H, I)
• CCIR 601, square pixel and 4Fsc operation
• 4:2:2 YCrCb and 4:1:1 YCrCb digital input formats
• Two on-chip 8-bit video DACs
• Internally generates SYNC and color burst signals
• Internal vertical interpolation filter
• Analog composite or Y/C output
• High-resolution mode supports Video CD, V2.0
• 16 CLUT RAM (programmable)
• Four modes of video/graphics operation:
graphics, video, chroma key and external key
• Color bar generation test function
• Suspend function
• 64-lead PQFP package
• Single +3.3 V power supply
GENERAL DESCRIPTION
The SPT2210 is a single-chip video encoder that is ca-
pable of converting digital video data (YCrCb) into analog
NTSC or PAL video signals. Two digital input formats are
supported: 4:2:2 (YCrCb) and 4:1:1 (YCrCb). It internally
generates the proper SYNC and color burst signals for
NTSC (525 lines/60 Hz) and PAL (625/50 Hz) video stan-
dards operating in any one of three sample rate modes:
CCIR 601, square pixel and 4Fsc.
Composite or Y/C S-Video analog video output is gener-
ated via two 8-bit internal video DACs. In addition, the
APPLICATIONS
• Video cameras
• Digital video tape recorders
• Video conference equipment
• Video frame grabbers
• Set-top boxes
• Video projection and displays
• Video printers
• Video game machines
• Multimedia PCs
SPT2210 supports external or chroma key functions for
color graphics pixel-by-pixel overlay. It has a 16-color
lookup-table overlay palette which is fully programmable.
It also has an on-chip vertical interpolation filter that can
be activated to reduce jaggy noise and flicker. The chip
also features an internal test color bar pattern generator.
The SPT2210 operates from a single +3.3 V supply and
is built in a 0.5 µm CMOS process. It is available in a 64-
lead PQFP package and operates over the commercial
temperature range.
BLOCK DIAGRAM
YD7…0
Vertical
Interpolation
CD7…0
Vertical
Interpolation
MUX
MUX
VRTENB
GD3…0
CLUT
16 x 16
KEY
KEY Logic
Interpolation
Interpolation
Y
Cr
Cb
MUX
Y
Cr
Cb
SYNC Generator
Y
Y
Level
Converter
Cr
Cr
LPF
SYNC/BLANK
Pedestal
Cb
Cb
LPF
DTO
MPU Interface
CS RS RD WR D7…0 Reset
VCS
DAC
Y/CVBS
DAC
C
VREF
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com