SII150A Datasheet, PDF (1/6 Pages) List of Unclassifed Manufacturers – PanelLink Digital Transmitter

SiI 150A
PanelLink^® Digital Transmitter
July 2000
General Description
As the universal transmitter, SiI 150A uses PanelLink Digital technology
to support displays ranging from VGA to SXGA (25-112 MHz). The SiI 150A
transmitter supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 or
2 pixels/clock mode, and also features an inter-pair skew tolerance up to 1 full
input clock cycle. An advanced on-chip jitter filter is also added to extend
tolerance to VGA clock jitter. Since all PanelLink products are designed on
scaleable CMOS architecture to support future performance requirements
while maintaining the same logical interface, system designers can be
assured that the interface will be fixed through a number of technology and
performance generations.
PanelLink Digital technology simplifies PC design by resolving many of
the system level issues associated with high-speed digital design, providing
the system designer with a digital interface solution that is quicker to market
and lower in cost.
Features
• Scaleable Bandwidth: 25-112 MHz (VGA to SXGA)
• Low Power: 3.3V core operation & power-down
mode
• High Skew Tolerance: 1 full input clock cycle (9ns at
108 MHz)
• Flexible panel interface: single or dual pixel in at up
to 24-bits
• Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
• Compliant with DVI 1.0 (DVI is backwards
compatible with VESA® P&D^TM and DFP)
SiI 150A Pin Diagram
DIFFERENTIAL
SIGNAL
DIO20 51
DIO19 52
DIO18 53
DIO17 54
DIO16 55
VCC 56
GND 57
DIO15 58
DIO14 59
DIO13 60
DIO12 61
DIO11 62
DIO10 63
DIO9 64
DIO8 65
IVCC 66
GND 67
DIO7 68
DIO6 69
DIO5 70
DIO4 71
DIO3 72
DIO2 73
DIO1 74
DIO0 75
SiI150A
100-Pin TQFP
(Top View)
Functional Block Diagram
25 PIXS
24 EDGE
23 RESERVED
22 RESERVED
21 RESERVED
20 RESERVED
19 PGND1
18 PVCC1
17 IVCC
16 DIE0
15 DIE1
14 DIE2
13 DIE3
12 DIE4
11 DIE5
10 DIE6
9 DIE7
8 VCC
7 GND
6 DIE8
5 DIE9
4 DIE10
3 DIE11
2 DIE12
1 DIE13
EXT_SWING
DIE[23:0]
DIO[23:0]
DE
HSYNC
VSYNC
CTL1
CTL2
CTL3
24
DATA
24
HSYNC
VSYNC
DATA
Data
Capture ^CTL1
Logic
DATA
CTL2
CTL3
EDGE
PIXS
IDCK
Jitter
Filter
Swing
Control
Encoder
0
Tx0
Tx0+
Tx0-
Encoder
1
Tx1+
Tx1
Tx1-
Encoder
2
Tx2+
Tx2
Tx2-
TxC+
PLL
TxC
TxC-
CONTROLS
GPI PLL
EVEN 8-bits RED
Revision C
Subject to Change without Notice