SII141 Datasheet, PDF (1/12 Pages) List of Unclassifed Manufacturers – SiI 141B PanelLink Digital Receiver

SiI 141B PanelLink^® Digital Receiver
May 2001
General Description
The SiI 141B uses PanelLink Digital technology to support displays
ranging from VGA to High Refresh XGA (25-86 MHz), which is ideal for LCD
desktop monitor applications. With a flexible single or dual pixel out interface
and selectable output drive, the SiI 141B receiver supports up to true color
panels (24 bit/pixel, 16.7M colors) in 1 pixel/clock mode (18 bit/pixel in 2
pixel/clock mode). PanelLink also features an inter-pair skew tolerance up to
1 full input clock cycle. The SiI 141B is pin for pin compatible with the SiI
141 but incorporates a number of enhancements. These include an
improved jitter tolerant PLL design, new HSYNC filter and power down when
the clock is inactive. All PanelLink products are designed on a scaleable
CMOS architecture to support future performance requirements while
maintaining the same logical interface. System designers can be assured
that the interface will be fixed through a number of technology and
performance generations.
PanelLink Digital technology simplifies PC design by resolving many of
the system level issues associated with high-speed digital design, providing
the system designer with a digital interface solution that is quicker to market
and lower in cost.
Features
• Scaleable Bandwidth: 25-86 MHz (VGA to High
Refresh XGA)
• Low Power: 3.3V core operation & power-down mode
• Automatic power down when clock is inactive
• High Skew Tolerance: 1 full input clock cycle (15ns at
65 MHz)
• Pin-compatible with SiI 101, SiI 141
• Sync Detect: for Plug & Display “Hot Plugging”
• Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
• Compliant with DVI 1.0 (DVI is backwards compatible
with VESA® P&D^TM and DFP)
SiI 141B Pin Diagram
24-bit Input Data for 1-pixel/clock mode
8-bit Channel 2 Data
1-pixel/clock
8-bit Channel 1 Data
1-pixel/clock
8-bit Channel 0 Data
1-pixel/clock
18-bit Even Data for 2-pixel/clock mode
6-bit Odd Channel 0
Data 2-pixel/clock
6-bit Even Channel 2
Data 2-pixel/clock
6-bit Even Channel 1
Data 2-pixel/clock
DE 41
Q20 42
Q21 43
Q22 44
Q23 45
OGND 46
Q24 47
OVCC 48
Q25 49
VCC 50
Q26 51
Q27 52
Q28 53
Q29 54
Q30 55
Q31 56
Q32 57
Q33 58
Q34 59
Q35 60
SiI141B
80-Pin TQFP
(Top View)
20 Q4
19 Q3
18 Q2
17 Q1
16 Q0
15 OVCC
14 VSYNC
13 OGND
12 HSYNC
11 GND
10 CTL3
9 CTL2
8 CTL1
7 SCDT
6 DFO
5 PIXS
4 OGND
3 PDO
2 PD
1 RESERVED
DIFFERENTIAL SIGNAL
MISC.
Subject to Change without Notice