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PEEL16V8P-15 Datasheet, PDF (1/10 Pages) List of Unclassifed Manufacturers – PEEL™6V8 -15/-25 CMOS Programmable Electrically Erasable Logic
Commercial
PEEL™16V8 -15/-25
CMOS Programmable Electrically Erasable Logic
Features
s Compatible with Popular 16V8 Devices
 16V8 socket and function compatible
 Programs with standard 16V8 JEDEC file
 20-pin DIP and PLCC packages
s CMOS Electrically Erasable Technology
 Superior factory testing
 Reprogrammable in plastic package
 Reduces retrofit and development costs
s Application Versatility
 Replaces random logic
 Super-sets standard 20-pin PLDs (PALs)
s ICC
 45mA typical ICC
s Development/Programmer Support
 Third party software and programmers
 ICT PLACE Development Software and
PDS-3 programmer
 Automatic programmer translation and
JEDEC file translation software available
for the most popular PAL devices
General Description
The PEEL16V8 is a Programmable Electrically
Erasable Logic (PEEL) device providing an attrac-
tive alternative to ordinary PLDs. The PEEL16V8
offers the performance, flexibility, ease-of-design
and production practicality needed by logic design-
ers today. The PEEL16V8 is available in 20-pin DIP
and PLCC packages (see Figure 1) with speeds
ranging from 15ns to 25ns and power consumption
less than 45mA. EE-reprogrammability provides the
convenience of instant reprogramming for develop-
ment and a reusable production inventory minimiz-
ing the impact of programming changes or errors.
EE-reprogrammability also improves factory test-
ability, thus ensuring the highest quality possible.
The PEEL16V8 architecture allows it to replace
standard 20-pin PAL devices. (See Figure 2). ICT’s
PEEL16V8 can be programmed with any existing
16V8 JEDEC file. Some programmers also allow
the PEEL16V8 to be programmed directly from PAL
16L8, 16R4, 16R6 and 16R8 JEDEC files. Addi-
tional development and programming support for
the PEEL16V8 is provided by popular third-party
programmers and development software. ICT also
offers free PLACE development software and a low-
cost development system (PDS-3).
Pin Configuration (Figure 1)
I/CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OE
DIP
I/CLK
I/OE
PEEL
"AND"
ARRAY
64 TERMS
X
32 INPUTS
Block Diagram (Figure 2)
CLK
MACRO
I/O
CELL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PLCC
3-7