M21L216128A Datasheet, PDF (1/14 Pages) List of Unclassifed Manufacturers – 128 K x 16 SRAM HIGH SPEED CMOS SRAM

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SRAM
FEATURES
T Fast access times : 10, 12, and 15ns
T Fast OE access times : 5, 6, and 7ns
T Single +3.3V ± 0.3V power supply
T Fully static -- no clock or timing strobes necessary
T All inputs and outputs are TTL-compatible
T Three state outputs
T Center power and ground pins for greater noise immunity
T Easy memory expansive with CE and OE options
T Automatic CE power down
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M21L216128A
128 K x 16 SRAM
HIGH SPEED CMOS SRAM
ORDERING INFORMATION
44-pin 400mil SOJ
44-pin 400mil TSOP (TypeII)
PRODUCT NO.
Acess Time
(ns)
M21L216128A-10J
10
M21L216128A-10T
M21L216128A-12J
12
M21L216128A-12T
M21L216128A-15J
15
M21L216128A-15T
PACKING
TYPE
SOJ
TSOP
SOJ
TSOP
SOJ
TSOP
GENERAL DESCRIPTION
The M21L216128A is a high speed, low power
asynchronous SRAM containing 2,097,152 bits and
organized as 131,072 by 16 bits, it is produced by high
performance CMOS process.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
problems, this device offers chip enable ( CE ), separate byte
enable controls ( LB and HE ) and output enable ( OE ) with this
organization.
PIN ASSIGNMENT
SOJ Top View
A4 ₁
A3 ₂
A2 ₃
A1 4
A0 5
CE 6
DQ1 7
DQ2 8
DQ3 9
DQ4 10
VCC 11
GND 12
DQ5 13
DQ6 14
DQ7 15
DQ8 16
WE 17
A16 18
A15 ¹⁹
A14 ²⁰
A13 ²¹
A12 ²²
44 A5
43 A6
42 A7
41 OE
40 HB
39 LB
38 DQ16
37 DQ15
36 DQ14
35 DQ13
34 GND
33 VC C
32 DQ12
31 DQ11
30 DQ10
29 DQ9
28 N C
27 A8
26 A9
25 A10
24 A11
23 N C
TSOP (TypeII) Top View
A4
1
A3
2
A2
3
A1
4
A0
5
CE
6
DQ1
7
DQ2
8
DQ3
9
DQ4
10
VC C
11
GND
12
DQ5
13
DQ6
14
DQ7
15
DQ8
16
WE
17
A16
18
A15
19
A14
20
A13
21
A12
22
44
A5
43
A6
42
A7
41
OE
40
HB
39
LB
38
DQ16
37
DQ15
36
DQ14
35
DQ13
34
GND
33
VCC
32
DQ12
31
DQ11
30
DQ10
29
DQ9
28
NC
27
A8
26
A9
25
A10
24
A11
23
NC
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0
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