M1T1HT18PZ32E Datasheet, PDF (1/6 Pages) List of Unclassifed Manufacturers – High Speed Pipelined 1-Mbit (32Kx32) Standard 1T-SRAM Embedded Memory Macro

High Speed Pipelined 1-Mbit (32Kx32)
Standard 1T-SRAM^® Embedded Memory Macro
M1T1HT18PZ32E
• High Performance 1T-SRAM Standard Macro
• 200 MHz operation
• 1-Clock cycle time
• Pipelined read access timing
• Late-late write mode timing
• 32-Bit wide data buses
• Byte Write Enables
• Simple standard SRAM interface
• Fast delivery
• Ultra-Dense Memory
• 3.8mm² size per macro instance
• Redundancy & fuses included in macro area
• Silicon-Proven 1T-SRAM Technology
• Qualification programs completed
• Products in volume production
• High Yield and Reliability
• Built-in redundancy for enhanced yield
• Standard Logic Process
• TSMC 0.18µm CL018G process
• Logic design rules
• Uses 4 metal layers
• Routing over macro possible in layers 5+
• Power
• Single voltage 1.8V Supply
• Low power consumption
adr[14:0]
din[31:0]
bweb[3:0]
rdb
wrb
clk
rstb
dout[31:0]
mvddcore
mvsscore
mvdd
mvss
General Description
The M1T1HT18PZ32E macro is a 1Mbit (1,084,576 bits), high speed, embedded 1T-SRAM macro. The macro
is organized as 32K(32,768) words of 32 bits. The macro employs a pipelined read timing interface with late
write timing. Write control over individual bytes in the input data is achieved through the use of the byte write
enable (bweb) input signals. The macro is implemented using MoSys 1T -SRAM technology, resulting in
extremely high density and performance.
M1T1HT18PZ32E Rev 2.doc
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