IDT77010 Datasheet, PDF (1/21 Pages) List of Unclassifed Manufacturers – Data Path Interface to Utopia Level 1 Translation Device

Data Path Interface (DPI) to
Utopia Level 1
Translation Device
IDT77010
Features
! _{Single chip ATM Layer UTOPIA Level 1 to 4-bit DPI interface.}
! _{Supports ATM Forum UTOPIA Level 1 interface.}
! _{Supports ATM device interface in Cell mode.}
! _{Capable of full-duplex operation up-to 160 Mbps.}
! _{Utility bus interface to access PHY registers.}
! _{In-stream control to access PHY registers.}
Description
The 77010 interfaces a UTOPIA PHY device to a device that uses a
Data Path Interface (DPI). Examples of PHY devices may include the
IDT77105, and the IDT77V400 Switching Memory is an example of a
component that utilizes a DPI interface. Figure 1 illustrates a typical
application using the IDT77010.
The UTOPIA level 1 bus interface runs at speeds up to 155 Mbps,
with the DPI-4 interface capable of full duplex operation at 160 Mbps.
In-stream programming is used to read and write to the PHY regis-
ters, with the Control Cells being generated from a remote controlling
agent. The Control Cells are used to configure, control and retrieve
status of the PHY device.
Theory of Operation
UTOPIA receive cells are transferred to the DPI-4 interface one cell
at a time. The DPI-4 clock rate is twice the frequency of receive UTOPIA
clock.
DPI-4 transmit cells are transferred to the UTOPIA transmit bus one
cell at a time. Transmit flow control is used to match the transmit cell rate
to the PHY's transmit cell rate.
Control cells are inserted and decoded by the control cell decoder.
The control cells are filtered and will not be transferred to the UTOPIA
transmit bus.
The control cell decoder block identifies the control cells and signals
the Utility Bus Interface to execute the commands. For a Utility bus write
command cell, the Utility bus does a one byte write to the specified
Utility bus address. For a Utility bus read command cell, the Utility bus
reads one byte from the specified Utility bus address and loads this byte
to the Cell Generator logic. The Cell Generator makes a request to the
receive cell arbiter to process the cell, and generates a status cell if no
UTOPIA receive cell is detected.
A status cell is a complete ATM cell generated and loaded to the
Receive DPI-4 I/F logic.
A receive cell on the DPI-4 bus is either an ATM cell from the receive
UTOPIA bus or a status ATM cell locally generated. Internally generated
ATM cells are output to the Receive DPI-4 Interface only when there are
no UTOPIA Receive cell. Figure 2 below shows the device data flow.
Block Diagram
OC-3
or
STS-3
OC-3
PHY
"
"
"
UTOPIA L1
Receive
IDT77010
UTOPIA L1
UTOPIA L1
Transmit
to DPI I/F
Utility bus
DPI Receive
4
4
DPI Transmit
Switching
Memory
"
IDT77V400 _.
"
"
Figure 1 Typical IDT77010 Application
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 2002 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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