HLX6228 Datasheet, PDF (1/12 Pages) List of Unclassifed Manufacturers – 128K x 8 STATIC RAM-Low Power SOI

Military & Space Products
128K x 8 STATIC RAM—Low Power SOI
HLX6228
FEATURES
RADIATION
• Fabricated with RICMOS^™ IV Silicon on Insulator
(SOI) 0.7 µm Low Power Process (L_eff = 0.55 µm)
• Total Dose Hardness through 1x10⁶ rad(Si)
• Neutron Hardness through 1x10¹⁴ cm^-2
• Dynamic and Static Transient Upset Hardness
through 1x10⁹ rad(Si)/s
• Dose Rate Survivability through 1x10¹¹ rad(Si)/s
• Soft Error Rate of <1x10^-10 Upsets/bit-day in Geosyn-
chronous Orbit
• No Latchup
OTHER
• Read/Write Cycle Times
≤ 32 ns (-55 to 125°C)
• Typical Operating Power <9 mW/MHz
• JEDEC Standard Low Voltage
CMOS Compatible I/O
• Single 3.3 V ± 0.3 V Power Supply
• Asynchronous Operation
• Packaging Options
– 32-Lead CFP (0.820 in. x 0.600 in.)
– 40-Lead CFP (0.775 in. x 0.710 in.)
GENERAL DESCRIPTION
The 128K x 8 Radiation Hardened Static RAM is a high
performance 131,072 word x 8-bit static random access
memory with industry-standard functionality. It is fabricated
with Honeywell’s radiation hardened technology, and is
designed for use in low voltage systems operating in radiation
environments. The RAM operates over the full military
temperature range and requires only a single 3.3 V ± 0.3V
power supply. The RAM is compatible with JEDEC standard
low voltage CMOS I/O. Power consumption is typically less
than 9 mW/MHz in operation, and less than 2 mW when de-
selected. The RAM read operation is fully asynchronous, with
an associated typical access time of 32 ns at 3.3 V.
Honeywell’s enhanced SOI RICMOS™ IV (Radiation Insensi-
tive CMOS) technology is radiation hardened through the use
of advanced and proprietary design, layout and process
hardening techniques.TheRICMOS™IVlow power process is
a SIMOX CMOS technology with a 150 Å gate oxide and a
minimum drawn feature size of 0.7 µm (0.55 µm effective gate
length—L ). Additional features include tungsten via plugs,
eff
Honeywell’s proprietary SHARP planarization process and a
lightly doped drain (LDD) structure for improved short channel
reliability. A 7 transistor (7T) memory cell is used for superior
single event upset hardening, while three layer metal power
bussing and the low collection volume SIMOX substrate
provide improved dose rate hardening.
Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • [phone] • http://www.myspaceparts.com