DF6811 Datasheet, PDF (1/9 Pages) Digital Core Design – 8-bit FAST Microcontrollers Family

8-bit FAST Microcontrollers Family
ver 2.08
OVERVIEW
Document contains brief description of
DF6811 core functionality. The DF6811 is a
advanced 8-bit MCU IP Core with highly so-
phisticated, on chip peripheral capabilities.
DF6811 soft core is binary-compatible with the
industry standard 68HC11 8-bit microcontrol-
ler and can achieve a performance 45-100
million instructions per second. DF6811 has
FAST architecture that is 3.8 times faster
compared to original implementation. Core in
standard configuration has integrated on chip
major peripheral function.
There are two serial interfaces: an asynchro-
nous serial communications interface (SCI)
and a separate synchronous serial peripheral
interface (SPI).
The main 16-bit, free-running timer system
has implemented three input capture lines,
five output-compare lines, and a real-time in-
terrupt function.
An 8-bit pulse accumulator subsystem can
count external events or measure external
periods.
Self-monitoring circuitry is included on-chip to
protect against system errors. A computer
operating properly (COP) watchdog system
protects against software failures. An illegal
opcode detection circuit provides a non-
maskable interrupt if illegal opcode is de-
tected.
Two software-controlled power-saving modes,
WAIT and STOP, are available to conserve
additional power. These modes make the
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DF6811 IP Core especially attractive for
automotive and battery-driven applications.
The DF6811 have built in the development
support features designed into DF6811. The
LIR signal is intended as a debugging aid.
This signal is driven to active low for the first
bus cycle of each new instruction, making it
easy to reverse assemble (disassemble) in-
structions from the display of a logic analyzer.
DF6811 is fully customizable, which means
it is delivered in the exact configuration to
meet users requirements. There is no need to
pay extra for not used features and wasted
silicon. It includes fully automated testbench
with complete set of tests allowing easy
package validation at each stage of SoC de-
sign flow.
CPU FEATURES
● FAST architecture, 3,8 times faster than
the original implementation
● Software compatible with industry standard
68HC11
● 10 times faster multiplication
● 16 times faster division
● 64 bytes of remapped System Function
Registers space (SFRs)
● Up to 16M bytes of Data Memory
● De-multiplexed Address/Data Bus to allow
easy connection to memory
● Two power saving modes: STOP, WAI
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