CXA3108Q Datasheet, PDF (1/2 Pages) List of Unclassifed Manufacturers – A New Age of Unified High-Frequency Analog and Digital Circuits Digital Satellite Broadcast Tuner IC

A New Age of Unified High-Frequency Analog and Digital Circuits
Digital Satellite Broadcast Tuner IC
CXA3108Q
CXA3038N
Satellite broadcasting using digital modulation first
entered service in 1994 in the US, and similar service
will begin this year, first in Europe and then in Japan.
Thus digital satellite broadcasting is expanding
rapidly on a worldwide scale. Sony has now developed
a chip set for the tuners of digital satellite broadcast
receivers. This chip set, which is introduced here,
consists of the CXA3108Q, which takes full advantage
of Sony's high-speed bipolar process technology and
integrates an oscillator/mixer circuit and a PLL circuit
for channel selection on a single chip, and the
CXA3038N quadrature detector IC.
CXA3108Q
s Supports an oscillator frequency of 2.7 GHz
s High gain and low noise figure
s On-chip channel selection PLL
(Supports both I²C bus* and 3-wire bus systems)
CXA3038N
s Adjustment-free carrier recovery provided by
an on-chip PLL circuit
s Minimal IQ quadrature error and minimal
amplitude error
* ForI²Cbus
PurchaseofSony'sI²CcomponentsconveysalicenseunderPhilips I²C
Patent Rights to use these components in an I²C system, provided that the
system conforms to the I²C Standard Specifications as defined by Philips.
On-Chip PLL Frequency
Synthesizer Circuit
<CXA3108Q>
The CXA3108Q integrates on a single
chip two functions that were previously
implemented on separate ICs: the
L-band down converter functions
(oscillator and mixer), and channel
selection. The PLL control function
supports both the I²C bus and the 3-wire
bus and allows an even wider range of
reference frequencies to be selected.
Support for a 2.7-GHz
Oscillator Frequency
<CXA3108Q>
The adoption of the newly-developed
P42 high-frequency linear process (fT
= 30 GHz), and the use of a Sony's
unique differential Colpitts oscillator
circuit allows this device to provide a
stable oscillator signal with no parasitic
oscillation over the wide band of 1.3 to
2.7 GHz. As shown in figure 3, the
frequency conversion characteristics of
this device are extremely flat and
feature high gain and low noise
figure.
VOICE
These products combine both
high-frequency/low-noise analog
circuits and high-speed digital
circuits in a single chip, and in-
corporate a wide range of tech-
niques for suppressing mutual
interference between these cir-
cuits. We are convinced that these
ICs will contribute to reduced
costs and significant miniaturiza-
tion in digital satellite broadcast
tuners.
Adjustment-Free
Carrier Recovery
<CXA3038N>
The CXA3038N provides adjustment-
free operation of the carrier recovery
function, which is required for 480-
MHz band quadrature detection by
including an on-chip PLL circuit.
External control is not required, since
the PLL circuit includes the divide data
and it can replace the high-cost SAW
resonator. Furthermore, to provide for
cases where the carrier frequency needs
to be adjusted, the device includes an
A/D converter to allow the frequency
to be adjusted over a range consisting
of ±4 50-kHz steps from the center fre-
quency of 479.5 MHz.
Support for a Wide Range of
Applications
The CXA3108Q provides two IF
output circuit systems and an external
input pin for the PLL circuit, and can
support applications such as single unit
tuners for both analog and digital satel-
lite broadcasts and tuners for both UHF
and VHF broadcasts. Since the
CXA3038N also includes an on-chip 32
frequency divider circuit for the local
oscillator signal, it can also support the
earlier carrier recovery technique, in
which a PLL circuit was included in the
QPSK demodulation IC used in a later
stage. The CXA3108Q and CXA3038N
have power consumption levels of 350
mW and 250 mW, respectively, and
achieve a significant power reduction
over most previous chip sets. This
makes these devices optimal for bit
stream output type tuner pack products
that implement, in a single unit, the
whole tuner up to the QPSK demodula-
tion and error correction circuit, which
requires consideration of the heat
generation problem.