CH7303 Datasheet, PDF (1/15 Pages) List of Unclassifed Manufacturers – Chrontel CH7303 HDTV / DVI Encoder

Chrontel
CH7303
Preliminary Advanced Information
Chrontel CH7303 HDTV / DVI Encoder
Features
General Description
• Digital Visual Interface (DVI) Transmitter up to 165M ^{The CH7303 is a Display Controller device which accepts a}
pixels/second
digital graphics input signal, and encodes and transmits data
• DVI low jitter PLL
• DVI hot plug detection
• Analog YPrPb outputs for HDTV
through a DVI link (DFP can also be supported), VGA ports
(analog RGB) or a HDTV port (YPrPb). The device is able to
encode the video signals and generate synchronization signals
for analog HDTV interface standards and graphics standards
• HDTV support for 480p, 576p, 720p, 1080i and 1080p _{up to UXGA. The device accepts data over one 15-bit wide}
• Macrovision^TM copy protection support for HDTV _{variable voltage data port which supports 9 different data}
• Programmable digital input interface supporting RGB formats including RGB and YCrCb.
(15, 16, 24 or 30 bit) and YCrCb input data formats
• Can output either RGB or YPrPb
• TV / Monitor connection detect
• Programmable power management
• Three 10-bit video DAC outputs
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Low voltage interface support to graphics device
The DVI processor includes a low jitter PLL for
generation of the high frequency serialized clock, and all
circuitry required to encode, serialize and transmit data.
The CH7303 is able to drive a DFP display at a pixel rate
of up to 165MHz, supporting UXGA resolution displays.
No scaling of input data is performed on the data output
to the DVI device.
• Offered in a 64-pin LQFP package
In addition to DVI encoder modes, bypass modes are included
• Backward pin compatible with CH7301 or CH7009/11 _{which perform color space conversion to HDTV standards}
• Support three additional 15 bit multiplexed RGB Input _{and generate and insert HDTV sync signals, or output VGA}
Data Format (IDF 6,7.8)
style analog RGB for use as a CRT DAC.
† Patent number 5,781,241
Â¥ Patent number 5,914,753
Note: Other names and brands may be claimed as property by others.
HPDET
GPIO[1:0]
AS
SPC
SPD
RESET*
H,V
2
DE
VREF
XCLK,XCLK*
2
D[14:0] ₁₅
ISET
Serial
Port
Control
/
24
H,V,DE
Latch
/
2
Clock
Driver
Data
Latch, /
Demux ³⁰
Color Space
/ Conversion
24 _{Sync Decode}
/
30
DVI PLL
DVI Encode
DVI
Serialize
DVI Driver
/ TLC, TLC*
2
/ TDC0, TDC0*
2
/ TDC1, TDC1*
2
/ TDC2, TDC2*
2
/ HSYNC,
2 _VSYNC
HDTV ^YPbPr
RGB
MUX
DAC 2
DAC 1
DAC 0
Three
10-bit DAC's
DAC[2]
DAC[1]
DAC[0]
Figure 1: Functional Block Diagram
209-0000-031 Rev. 0.4, 8/26/2002
1